JPS6023551B2 - Digital signal communication method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal communication method for transmitting and receiving signals via a buffer memory.

In digital communications, signals on the transmitting side or in cases where they occur irregularly are normally transmitted and received via a buffer memory to smooth the signals on the transmission path before communication.

One example of such communication is an interframe coding method that performs transmission by determining the correlation between frames of image signals. The capacity of the buffer memory of the interframe encoding device is determined at the time of system design, depending on the required surface quality and the form of the transmitted code.

Normally, the capacity of the buffer memory is determined based on the amount of data that can be transmitted in one frame time so that the data for one frame time is smoothed and the decoder on the receiving side is operated with a delay of one frame time.

For example, in an encoder that performs transmission at 6.312 Mb/s, the situation is as follows.

In standard television, this is 30 frames/second.

Therefore, the minimum required capacity of the buffer memory of the encoder is S = 211 [Kbit] Halm).

Further, the code format transmitted based on the hardware element speed is generally configured as shown in FIG. 1, stored in a buffer memory as a fixed length, and variable length encoding is performed on the output side.

In this figure, 1 is a transmitting side buffer memory, 2 is a variable length encoder, 3 is a variable length decoder, 4 is a receiving side buffer memory,
A is a frame synchronization position identification signal (in this example, an image frame synchronization position identification signal) insertion position; B is a transmitting side encoder synchronization signal F, insertion position; C is a receiving side encoder synchronization signal F
2 extraction position, D is the (video) frame synchronization position identification signal readout position, Ms is the transmitter/buffer memory content capacity, M
R indicates the content capacity of the receiving side buffer memory, and aR indicates the average code length of one frame time. In a communication system such as this example, the capacity of the buffer memory is determined by the variation in the average code length of variable-length transmission codes over one frame time.

Here, the average code length refers to the average length of codes generated in one frame. That is, in this example, signals are transmitted by using codes with different code lengths, and the unit of code length in this case is [bit/word].

For example, if the average code length variation is 1.5 to 4.1, then 1
If the amount of information that can be transmitted in a video frame is F, and the bit rate of the transmission path is 6.312 Mb/s, Ms+
MR=F/aR.

Therefore, F=Kigaku type arrow=211Kbit becomes.

Here, the size of the transmission buffer memory is Msmax=211/4.1≠ when MR≠0 and the average code length is 4.1.
50 kilowords (hereinafter referred to as KW), and the size of the receive buffer memory is M if the average code length is 1.5 and Ms≠0.
Rmax=211/1.5=1maleboard W is selected.

Therefore, in a system that operates with the frame phases of the transmitting and receiving encoders synchronized, if the transmitting and receiving encoders are controlled using a single frame synchronization identification code as in the conventional method, the initial operation will depend on the average code length. As shown in FIG. 2, there are three stable read positions of the receiving side buffer memory: a, b, and c. Conditions b and c are cases in which the average code length is relatively long, and in b, transmission data for a total of 2 frame periods are stored, and in c, transmission data for a total of 3 frame periods is stored. In these states, when the average code length becomes shorter, the number of words that can be transmitted in one frame time increases, and the content capacity of the receive buffer memory increases, causing an overflow state and transitioning to state a. In such a case, the image quality is significantly degraded due to overflow, which is not practical. In general, even in interframe coding systems that have a buffer memory of ○ (≧ 1) frame time or more, exactly the same problem occurs during the pull-in process on the receiving side, and stable control cannot be achieved with a single synchronization identification code such as a follower. cannot be done.

The purpose of the present invention is to eliminate the above-mentioned problems, thereby making it possible to always provide stable operation. The configuration of the present invention for achieving the above object is that in a digital signal communication system that transmits and receives via a buffer memory, n frame synchronization position identification signals (nZ2) are provided at a plurality of positions in the digital signal, and the transmitting side buffer From the input side of the memory, the frame synchronization position identification Si (i=1, 2, . . .
n) and decoded from the Si (i=i−○, D: natural number) frame synchronization position identification signal on the output side of the receiving side buffer memory.

The present invention will be described below by taking as an example a system in which the buffer memory uses fixed-length words and transmission uses variable-length codes. To simplify the explanation, an example will be described in accordance with FIG. 4 in which the transmission delay time described earlier is assumed to be one frame, and the variation in average code length is 1.5 to 4.1 bits.
FIG. 4 is a block diagram of an embodiment of the present invention.

A time chart for explaining this embodiment is shown in FIG. In Fig. 3, S,, S2, S3 are frame synchronization identification signals, 1 is the transmitting side, 0' is the timing of the receiving side, (
ll is the encoder synchronization signal insertion timing, (ii) is the frame synchronization identification signal insertion timing, (iiD is the encoder synchronization signal extraction timing, and GW is the frame synchronization identification signal decoding timing. In FIG. 4, 1, 2, 3, 4
and A, B, C, 0 indicate the same parts and positions as in FIG.

5 is a frame synchronization position identification signal insertion circuit, 6 is a data code conversion circuit, 7 is a multiplexing circuit, 8 is an encoder synchronization signal insertion circuit, 9 is an encoder synchronization signal extraction circuit, 10 is a decoder clock circuit, 11 is a separation decoding circuit, 12 is a frame synchronization position identification signal reading circuit, and 13 is a data decoding circuit.

The frame synchronization identification signals S, , S2, and S3 are timed with the frame synchronization insertion instruction signal, and are sequentially cyclically inserted starting from A.

On the receiving side, upon detecting encoder synchronization, decoding is started at S3 using a read clock supplied from a clock circuit set to operate in synchronization with the transmitting side encoder. In the figure, S indicates the transmitting side and R indicates the receiving side, and an insertion instruction pulse is input to the frame synchronization layer identification signal insertion circuit at a predetermined timing, and at A, the signals S, , S2, and S3 illustrated in FIG. is inserted.

This identification signal is multiplexed together with the output from the data code conversion circuit 6 in the multiplexing circuit 7, and the buffer memory 1
, the variable length encoder 2, and the encoder synchronization signal insertion circuit 8 to the transmission path. Note that the insertion instruction pulse also instructs the encoder synchronization signal insertion circuit 8 to generate a synchronization signal for maintaining the transmitting side S and the receiving side R in a constant positional relationship. On the receiving side, an encoder synchronization signal extraction circuit 9 extracts a synchronization signal, and provides a reset pulse to the decoder clock circuit 10 at a predetermined timing at this synchronization position. The decoder clock circuit 10 generates a timing signal and supplies it to the frame synchronization position identification signal reading circuit 12 and the data decoding circuit. On the other hand, the data signal is inputted to a frame synchronization position identification signal reading circuit 12 and a data decoding circuit 13 via a variable length decoder 3, a buffer memory 4, and a separation decoding circuit 11. When a predetermined pulse position is detected in the frame synchronization position identification signal reading circuit 12, a pulse is given to the data decoding circuit to start decoding. In conventional decoder control using a single identification code, there are cases where the sum of the contents of the transmitting and receiving buffer memory becomes 1 frame time, 2 frame time, or 3 frame time depending on the average code length at the start, but this method You can always set it to 1 frame time.
The reason is shown below. Since the counter on the receiving side moves in synchronization with the transmitting side by the synchronizing code of the encoder inserted from the output side of the transmitting buffer memory, the total content capacity of the transmitting and receiving memory does not exceed the capacity for three frames.

However, as shown in Figure 3, the state in which S, is input to the transmitting buffer memory stream in synchronization with the synchronization code of the encoder, and S3 can be decoded from the buffer memory on the receiving side is as shown in Figure 3.
4,...The frame time becomes 1, and the stable state is 1 from the previous condition.
Frame time only.

According to the present invention, the frame synchronization position identification signal Si (i=1
, 2, .

If (i-D) becomes negative, Sj appears in the sequence, so Sj becomes j=n+(i-D). Although the present invention has been explained above using fixed length storage and variable length transmission as examples, it can be applied in exactly the same way to the case where the decoder on the receiving side operates stably by delaying the D frame time to improve image quality. is clear.

[Brief explanation of drawings]

Fig. 1 shows an example of a communication system to which the present invention is applied, Fig. 2 shows the storage capacity state of the buffer memory, Fig. 3 is a time chart for explaining the present invention, and Fig. 4 shows an embodiment of the present invention. Give an example. In FIGS. 1 and 4, 1 is a transmitting side buffer memory, 2 is a variable length encoder, 3 is a variable length decoder, and 4 is a receiving side buffer memory. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. In a digital signal system that transmits and receives via a buffer memory, 1 to n frame synchronization position identification signals are provided cyclically for n consecutive frame synchronization signals (n≧2) inserted into the digital signal. , the frame synchronization position identification signal Si (i=1, 2,..., n,) is sent from the input side of the transmitting buffer memory, and Sj (j=i-D, D: natural number) is sent from the output side of the receiving buffer memory. A digital signal communication method characterized in that decoding is performed from the th frame synchronization position identification signal.