JPS6024436B2 - Electronic clock with stopwatch - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece with a stopwatch that has a digital display section and is capable of measuring time for a sufficiently long time when the number of displayed digits is limited.

In response to the development of numerical display means, various methods of electronically performing timekeeping operations and displaying the time and the like digitally came to be known as digital display clocks. In particular, miniaturized timepieces such as wristwatches are also being developed as electronic type watches with digital displays using liquid crystal display means. However, when displaying the time etc. digitally using numerical values, there are restrictions on the size of the displayed characters to make it easy to determine whether to continue, and there are restrictions on the area of the display panel. There is a limit to the number of display digits. This is not limited to watches, but also when trying to configure a time measurement device such as a stopwatch with a digital display.
This is a drawback that occurs, for example, it becomes difficult to clearly measure time over a sufficiently long period of time down to small units.

In particular, when a stopwatch is configured in combination with a digital display type clock, it is necessary to display the stopwatch measurement time using the time display section of the clock, which makes it impossible to display time measurement over a wide range. This invention was made in view of the above points, and it is possible to display time measurement results with a sufficiently wide measurement range using a digital display section with a limited number of digits, and is suitable for use in miniaturized watches such as wristwatches. It is an object of the present invention to provide an electronic timepiece with a stopwatch that can be effectively combined and configured even when using a stopwatch.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 11 is an oscillation circuit that oscillates a reference clock signal. The reference clock signal from this oscillation circuit 11 is supplied to frequency dividing circuits 12 and 13, respectively.
The frequency dividing circuits 12 and 13 each generate a count signal of one pulse per second (lp/ls). In this case, the frequency dividing circuit 12 has lp/ls as described above.
Along with the signal, clock pulses for controlling other circuits ◇
The frequency divider circuit 13 also serves as a timing circuit that generates JB, and when the set signal is connected, as will be described later, it is in the reset state and does not generate an output for a minute, and when the reset signal is disconnected. When this happens, the signal from the oscillation circuit 11 is started to be counted, and a frequency-divided output is generated. The lp/ls counting signal from the frequency dividing circuit 12 is coupled to the counting circuit 14 of 1 Bo Hayabusa as a counting step command. Hayabusa, hexadecimal, decimal counting times Iso 15, 16, 17,
18 are combined and sequentially incremented by the carry signal.

That is, the counting circuits 14 and 15 count the units of seconds, the counting circuits 16 and 17 count the units of minutes, and the counting circuit 18 counts the units of hours. The counting circuits 14 to 18 constitute a clock counting circuit 19. Further, the signal from the frequency dividing circuit 13 is transmitted to the AND circuit 2.
1G ships set up in cascade in the same way as above 6
Shin, 1 Bobee Hexadecimal, 1 dollar boat counting circuit 21, 22, 23
, 24, 25. Then, the counting circuits 21 and 22 are set to "second", and the counting circuit 23,
24 corresponds to "minutes" and the counter circuit 25 corresponds to "hours", respectively, and the frequency division signal from the frequency division circuit 13 is made to count. Then, the clock value signals of the counting circuits 16 to 18 corresponding to "minutes" and "hours" of the clock counting circuit 19 are supplied to the first AND gate group 27, and Counting circuits 21 to 24 corresponding to "seconds" and "minutes" in the section count value signals are sent to the second AND gate group 28.
Similarly, the counter clock value signals of the counting circuits 23 to 25 corresponding to "minutes" and "hours" of the upper digit units are respectively coupled to the third AND gate group 29, and the clock value signals from these AND gate groups 27 to 29 are respectively coupled to the third AND gate group 29. The signals are coupled to the OR gate group 301.

The signal from this OR gate group 30 is supplied to a decoder drive 31, and the upper and lower digit parts are each
A digital display device 33 composed of numerical digits 32a and 32b is driven to display. The AND gate groups 27 to 29 are controlled by a display control switch 34, and an inverter 36 connected to this switch 34 provides a gate signal to the first AND gate group 27.

Further, the second AND gate group 281 supplies the signal when the switch 34 is turned on as a gate signal via the AND circuit 36 and the OR circuit 37, and the third AND gate group 29 supplies the signal when the switch 34 is turned on and the signal when the switch 34 is turned on. The gates are opened when the set power signals of flip-flop circuit 38, which will be described below, are coupled together. An inverter 39 is connected to the set power terminal of the flip-flop circuit 38, and the output signal of the inverter 39 is transmitted to the AND circuit 36.
as a gate signal. Further, a timer 40 is provided which is started when the switch 34 is turned off from the closed state, and generates an output signal from the timer 40 which is set after the switch 34 is opened, and the flip-flop circuit 38 is set. The output signal from the AND circuit 41 is coupled to the OR circuit 37 together with the output signal. An inverter 42 is connected to the output side of this AND circuit 41, and this inverter 42 is connected to the AND circuit 4 to which the output signal of the inverter 35 is coupled.
The gate signal of the first AND gate group 27 is opened by the output signal of the AND circuit 43. The flip-flop circuit 38 is set by a detection signal from a count "2" detection circuit 44 provided in the counting circuit 24 for counting the upper digit part of "minutes J" of the counting circuit 26. Further, this device is provided with a single switch 45 for time measurement control, and the switch 45 is turned on when pressed by a pusher or the like (not shown).

The operation signal of this switch 45 is supplied to the input control circuit 46.
One pulse signal is extracted in response to one operation of the switch 45, and this pulse signal from the input control circuit 46 is supplied as a count step signal to the control counter 47, and the count value is A count value output of 0, 1, and 2 is obtained. The "01" count value output signal of the control counter 47 is given as a reset signal to the frequency dividing circuit 13, the counting circuits 21 to 25, and the flip-flop circuit 38, and the "1" count value signal is given to the AND circuit 20.
It is combined and provided as a gate signal. FIG. 2 shows a specific example of the configuration of the input control circuit 46 and control counter 47. When the switch 45 is turned on, the signal S is written in by the clock pulse 4^ and is read out by the OB from the delayed flip-flop. The output signal of the delay circuit 48 and the delay circuit 49 are connected in series to the delay circuits 48 and 49.
The output signal of the inverter 50 connected to the output side of the clock pulse J^ is given to the AND circuit 51 as a gate signal.
It becomes like taking it out.

That is, assuming that the clock pulses ME^ and OB are generated at different timings as shown in FIG. The output signals of the inverter 50 are also shown in FIGS. 3a and 3b.
As a result, the clock signal pulse ? from the AND circuit 51 as shown in c of the same figure. One pulse signal corresponding to A is extracted. Further, the control counter 47 is written with the clock pulse ◇^ from the AND circuit 51, and the delay circuits 52 and 53, which are set to the read state with the clock pulse OB, are set in a series state, and the output signals of the delay circuits 52 and 53 are are combined with an OR circuit 54.

An inverter 55 is connected to the output terminal of this OR circuit 54, and the output signal of this inverter 55 is transferred to a delay circuit 52.
The output signal of the inverter 55 is fed back to the input side of the inverter 55 with "0" as the counting output, and the delay circuit 52,
The respective output signals of 53 are taken out as counting output signals of "1" and "2". That is, each time the switch 45 is operated, a clock pulse is generated from the input control circuit 46. One pulse output corresponding to
”, “10”, and “01”, and count value signals of “0”, “1”, and “2” are obtained in sequence.

That is, in the apparatus configured as described above, the clock counting circuit 19 divides and counts the reference clock pulse from the constant oscillation circuit 11 to perform a clock counting operation.

Further, in normal times, the display control switch 34 is in the crossroad state and the output signals of the inverters 35 and 42 are in the "1" state, so a gate signal is given to the AND gate group 27.
The clock count signal of the clock count circuit 19 is supplied to the decoder drive 31 via the OR gate group 30 and displayed on the display device 33.
The display sections 32a and 32b digitally display the time in hours and minutes. Here, if you want to perform a clock measurement operation like a stopwatch and display the measurement results, turn on the switch 34, and turn on the switch 45.
gives a start command for clock measurement. In this case, in the initial state, the control counter 47 is in a state where it generates a "0-1 count signal," the frequency divider circuit 13, the counting circuit 26, and the flip-flop circuit 38 are in a reset state, and the switch 45 is not operated. As a result, the control counter 47 generates a 1-count output, releases the reset state of the frequency divider circuit 13 and the counting circuit 26, and opens the gate of the AND circuit 20 to start counting. In this case, since the display control switch 34 is turned on and the flip-flop circuit 38 is in the reset state, the gate signal of the second AND gate group 28 is given from the AND circuit 36, and the display sections 32a and 32b of the display device 33 display the above calculation. "minute" of clock number
and "second" units will be displayed. Here, if the display device 33 is configured to display the time effectively, the display section 33 corresponding to "hour"
2a can only display numerical values up to a maximum of ``19'', and ``
The display section 32b corresponding to "minutes" can only display up to "59".

That is, "minutes" and "seconds" are displayed on the display sections 32a and 32b.
When the measurement time is displayed, the maximum time is "19 minutes 5 current sand"
Time measurement and display can only be performed up to. In this way, time measurement continues, and when the time reaches "20 minutes", which exceeds the display limit of the display device 33, this is detected by the detection circuit 4.
4 and the flip-flop circuit 38 is set.

That is, the gate of the AND circuit 36 is closed, the gate of the second AND gate group 28 is closed, and the gate of the third AND gate group 29 is opened, and the display device 33 displays the "minute" of the counting circuit 26. and “hour” counting circuit 23~
The display device 33 is controlled to display the count value of 25 using a signal, and time measurement and display are performed in units of "hour" and "minute". Then, the clock measurement display up to the maximum "1st period time 59" is performed. This time measurement state continues until the switch 45 is turned on the next time, and the second operation of the switch 45 causes the control counter 47 to generate a ``21 count signal''. The gate of AND circuit 20 is closed.

That is, this second operation of the switch 45 serves as a stop command, and the measured time corresponding to the interval between the first and second operation of the switch 45 is displayed on the display device 33.
Here, if the measured time is within the above-mentioned "19 minutes and 59 minutes", the measured time to the second unit is displayed on the display device 33.
If the measurement time exceeds this, the upper unit digits of the hours and minutes of the measurement time will be displayed on the display 3.
It is displayed as 3.

When the display control switch 34 is turned on in this state where the upper unit digit is displayed, the gates of the third AND gate group 29 are closed, and for the time set by the timer 40, the AND circuit 41 outputs the second AND gate. A gate signal is given to the group 28 to display the lower unit digit part of the measurement time on the display device 33, and after the time set by the timer 40, the gate of the first AND gate group 27 is opened and the clock counting circuit 19 is used to display the time. The above explanation is for the case where the time display is switched to the time measurement display, the time is measured, and then the time display is returned again.
If the time measurement lasts for a long time, it may be possible to return to the time display after the start. However,
In such a case, if it is less than 59 seconds after the start, the flip-flop circuit 38 is still in the reset state, and the gate of the AND gate group 28 is opened by operating the switch 34. " and the measured time in seconds are displayed immediately. Furthermore, if the time has exceeded "19 minutes 59 sand" since the operation of the switch 34 was started, the flip-flop circuit 38 is already in the set state, so the gate of the AND gate group 29 is opened. , the measured time in "hours" and "minutes" will be displayed, allowing you to immediately know the necessary information.
In the above embodiment, the counting signal displayed on the display device 33 is taken out by selectively switching the counting circuits 21 to 25, and the display digits are switched. , the counting circuit that obtains the count signal coupled to the display device 33 may be specified.

That is, as shown in FIG. 4, the counting circuit 2 for counting
1, 22 and 23 to 25 are divided into two to form the first and second counting circuits 26a and 26b, and the count value signals of the counting circuits 23 to 25 are sent to the second AND gate group 28. The count value signal of the counting circuit 217 22 is led to the AND gate group 29 of 3.

The frequency divided output from the frequency dividing circuit 13 is supplied to the counting circuit 21 and the AND circuit 56, and the carry signal of the counting circuit 22 is supplied to the AND circuit 57.
The signals from 6 and 57 are passed through the OR circuit 58 to the counting circuit 2.
3 as a counting step signal. A gate signal is coupled to the AND circuits 56 and 57 when the control counter 47 is counted, and a gate signal is applied to the AND circuits 56 and 59 when the flip-flop circuit 38 is reset, and to the AND circuit 57 when the flip-flop circuit 38 is set. In this case, the flip-flop circuit 38 is triggered inverted by the carry signal from the counting circuit 25, and the output of the AND circuit 59, which combines the trigger signal and the reset output signal, causes the flip-flop circuit 38 to be driven by the carry signal from the counting circuit 25. and gives a set command of "12". When the display control switch 34 is in the ON state, a gate signal is given to the second AND gate group 28, and the output signal of the timer 40 is used to give a gate signal to the third AND gate group 29.Other components are the same as those in FIG. are given the same reference numerals and their explanation will be omitted. That is, in this device as well, in the initial state, the control counter 47 is in a "0-1 counting state," and the flip-flop circuit 38 is also in a reset state.

and. When the signal S is obtained by operating the switch, the control counter 47 enters the "11 counting state," the frequency dividing circuit 13 starts frequency dividing operation, and the first counting circuit 26a starts counting the frequency divided signal. In addition, since the gate of the AND circuit 56 is also opened, the second counting circuit 26b also counts in parallel, and the counting circuits 23 to 25 calculate the seconds and seconds.
The clock will be measured in minutes. Here, if the display control switch 34 is turned on, the above-mentioned counting circuit 26b
It is coupled to the decoder drive 31 via the count signal and the second AND gate group 28, and the clock measurement time is displayed on the display device 33 in units of "seconds" and "minutes."

When such time measurement progresses and exceeds "19 minutes and 59 seconds", a carry signal is generated from the counting circuit 25, triggering the flip-flop circuit 38 and setting it in the set state. At the same time, an output signal is generated from the AND circuit 59 in response to the carry signal, the carry signal is generated, and when the carry signal is generated, the count value becomes "0" and the count value of the counting circuit 24 becomes "2". set. in this case,
The other counting circuits 21, 22, 23, 25 all have a count value of "0".
"As the flip-flop circuit 38 is set, the gate of the AND circuit 56 is closed, the gate of the AND circuit 57 is opened, the counting circuits 21 to 25 are set in cascade, and the counting circuits 23 to 25 are set in cascade. 26 comes to correspond to the units of "minute" and "hour", and the display device 33 comes to display "0 hours 2 minutes". From then on, the measured time will be displayed in hours and minutes. That is, on the display device 33, the display unit digits are switched and displayed according to the measurement time, as in the above embodiment. When the display control switch 34 is opened, a signal is generated from the timer 40 for a predetermined period of time, the gate of the third AND gate group 29 is opened, and the lower units of the measured time are switched and displayed.
After the set time has elapsed, the first AND gate group 27 is opened and the time is displayed on the display device 33.

In the above embodiment, the highest numerical value on the display section 32a is "19", but it may be "99".

Further, although the specified counting time for switching the display unit is set to "1 scale and 59 sands", this can also be set arbitrarily. Also, when measuring for a long time, after displaying the upper digits,
Display switching is controlled so that the lower digit part is displayed only for a specified time and the measurement time is not displayed thereafter, but this may also be done by displaying an arbitrary switching command, or in the case of long-term measurement. The display of the lower digits may be omitted. Furthermore, although the time measurement is controlled by a single switch 45 and the settings are made to sequentially switch between start, stop, and reset, it is also possible to restart from a stopped state as appropriate by setting the control counter 47 or other switches. Of course, it is also possible to control the transition.
In addition, it is possible to measure time of 1 second or less, and it goes without saying that various changes can be made without departing from the gist of the invention. As described above, according to the present invention, time can be effectively measured from a lower time unit than the time displayed using a specified digital display device for displaying the time. ,
It is highly effective when combined with a wristwatch or the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating a time measuring device according to an embodiment of the present invention, FIG. 2 is a diagram showing the control counter section of the above embodiment, and FIG. 3 is an illustration of the operation of the counter section. The signal waveform diagram in FIG. 4 is a configuration diagram illustrating another embodiment of the present invention. 11... Oscillation circuit, 12, 13... Frequency dividing circuit, 14-18, 21-25... Counting circuit, 1
9... Clock counting circuit, 26... Counting counting circuit, 27-29... AND gate group, 33...
...Display device, 34...Display control switch, 38...Flip-flop circuit, 45...
・Switch, 46... Input control circuit, 47...
control counter. Figure 2 Figure 3 Figure Dimensions of the ship

Claims (1)

[Claims] 1. A time counting means for obtaining time information by counting reference clock pulses, a display device for displaying the time information obtained by the time counting means, and a clock signal having a predetermined period for counting and measuring based on start/stop commands. An electronic watch comprising a time measuring means for obtaining time information, and a display control means for switching and displaying the measured time information obtained by the time measuring means on the display device by operating a switch,
The time measuring means counts measured time information including time units of lower digits than the lowest digit of the time information displayed on the display device, and detects that this measured time information has reached a specific value. The display control means includes a first display control means for displaying measurement time information including a time unit of the lower digit, and a measurement time including a time unit higher than the time unit of the lower digit. a second display control means for displaying information, and when the switch operation is performed, either the first display control means or the second display control means is controlled based on the storage contents of the storage means. An electronic timepiece with a stopwatch, characterized in that the electronic timepiece is selected and displayed on the display device.