JPS6024491B2 - Address conversion control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address translation device in an information processing system that implements a virtual storage system, and is capable of varying the size of a page, which is a basic unit of address translation.

In general, in information processing devices, the central processing unit uses logical addresses as they are, so that programs do not need to be aware of the main memory, and in order to implement virtual memory, and when accessing the main memory, logical addresses are used as is. This is done using the converted real address, and a conversion table from logical addresses to real addresses for this purpose is stored in the main memory.

Furthermore, referring to the conversion table every time the main memory is accessed is inefficient because the main memory is slower than the processing speed of the central processing unit. Therefore, in order to improve processing speed, a TLB (Train ship l
ationUmkasideBuffer), and address translation is performed by the TLB. When accessing the main memory for a logical address that is not stored in the TLB, it is converted to a real address using a conversion table on the main memory, and the conversion pair is newly stored in the TLB. Stored.

Such conversion from a logical address (virtual address) to a real address is performed for a page address.

The main storage device is divided and managed in page units, and data and programs on the external auxiliary storage device are stored in page units at predetermined addresses. Therefore, the logical address space (virtual address space) used by the program is also divided into page units and associated with the main storage device in page units. In this case, it is not necessary that the entire program be loaded into the main memory, but only the pages required for execution may be loaded.

In conventional information processing devices using virtual memory,
The size of this page can be the minimum size determined by the hardware configuration, for example 512 bytes, or an integral multiple of 512 bytes, for example 2 times (
1024 bytes = 1 page), 4 times (204 bytes = 1 page), or 8 times (4096 bytes = 1 page)
It was fixed in a fixed manner.

If the size of one page is to be doubled or quadrupled, for example, it is necessary to change the design of the hardware of the address translation device, modify it based on the design change, and add hardware. When actually operating an information processing device, it is easy to imagine that depending on the type of program, it may be possible to improve address conversion efficiency by changing the size of this page and performing address conversion.

However, conventional devices have a drawback in that in order to improve the efficiency of address translation by changing the page size, it is necessary to change the design, modify, or add hardware.

The present invention attempts to eliminate the drawbacks of conventional devices by making it possible to change the size of a page without changing the design, modifying, or adding hardware. This will be explained below based on the drawings.

FIG. 1 is a block diagram showing the operation of a conventional address translation device that does not arbitrarily change the page size.

1 indicates the bit width of the virtual address and its contents.

If we assume that the size of the smallest page determined by the hardware configuration is 512 bytes, and we have 3 pages as virtual storage space, we will use a bit to indicate the virtual page number. The width is 15 bits, and the bit width for indicating 512 bytes in one page is 9 bits, requiring a total width of 24 bits, and FIG. 1 shows this case.

2 in the figure represents the boundary between the 9-bit width and the 15-bit width. Further, in the figure, the number enclosed in a circle attached to the wavy line drawn intersecting the line indicating the signal path represents the bit width of the passing signal. First, when a virtual address is accessed by a programmer, a bit-width signal 3 indicating a virtual page number in the virtual address accesses the TLB. A correspondence table between virtual addresses and real addresses of frequently used pages is registered in the TLB from an address conversion table for converting virtual addresses to real addresses. Therefore, if the correspondence is registered, the real address instruction signal corresponding to the accessed virtual page number is output as 6. 7 is the bit width of the real address and its contents, which is 24 bits wide like the virtual address.

The upper 15 bits contain a real address instruction signal from the TLB, and the lower 9 bits contain a signal 5 indicating an in-page address from the virtual address 1 as is. Since the intra-page address is the same whether it is a virtual address or a real address, it can be used as is without any processing. In the end, since a 24-bit real address signal is held in 7, access to the main memory device is performed using this real address signal. When the main memory is accessed, access information is stored in the memory key corresponding to the actual page number of the main memory.
If the above address conversion using the TLB is not successful, it means that the TLB does not contain the virtual address to real address correspondence table required by the program, so the TLB does not contain the desired virtual page number. The correspondence between the page number and the actual page number must be stored. this is,
This is done by extracting the correspondence between the target virtual page number and real page number from the address translation table on the main memory and registering it in the TLB. The above is an explanation of address conversion in the case where the size of one page is fixed, for example, 512 bytes, which is determined by the hardware configuration. In contrast, the present invention provides address conversion by making it possible to arbitrarily change the page size to an integral multiple of the basic size determined by the hardware configuration without modifying or increasing the hardware. The aim is to increase the conversion efficiency of

Hereinafter, an example of how to update the page size and an example of address conversion using the updated TLB will be described with reference to the drawings.

FIG. 2 is a diagram showing the process of updating the TLB page size.

1 is the bit width of the virtual address and its contents, 8 is the address translation table (ACT), 9 is the bit width indicating the real page number, and 4 is the TLB.

In this figure, as an example, a case will be described in which the page size is updated to four times 512 bytes (204 & bytes). Although the page size is quadrupled, the number of virtual address pages is reduced to one-fourth, and the number of addresses within the page is quadrupled. Therefore, the bit width required to designate a virtual page number is reduced by 2 bits, whereas the bit width required to designate an intra-page address increases by 2 bits. This means that the virtual address bit width is 1
This means that the boundary 2 between the virtual page number in the page and the address in the page is moved to the left by 2 bit width compared to the case in FIG.

As a result, the bit width of the virtual page number is 13 bits, and the bit width of the intra-page address is 11 bits. First of all,
When a virtual page number is specified by the program, signal 13 is activated.
The address translation table (ACT) of 8 is accessed as follows.

Since the size of the page of the program is used as the real page number in ACT, the real page number taken out as signal 11 from ACT is also a 13-bit signal. However, since it is necessary to register in the TLB with a page size determined by the hardware configuration, the upper two bits of the in-page address of 1 are extracted as signal 10, and this is used as the real page number from ACT. By adding this to the lower part of the bit width, a 15-bit width real page number signal is created. On the other hand, when extracting the virtual page number from 1, not only the 13-bit virtual page number but also the upper 2 bits of the intra-page address are extracted and added to the TLB as the 15-bit virtual page signal 14. . In the end, a virtual page number of 512 bytes per page is added as a signal to the TLB, and a real page number of 512 bytes per page is also added as signal 12, and a correspondence table of real page numbers corresponding to virtual page numbers is added. will be registered. Third
The figure shows the updated page size T
This is used when address translation is performed by LB. This is a diagram. The only difference from Figure 1 is that the boundary 2' between the virtual page number in the virtual address and the address in the page has been moved by 2 bits to the left in Figure 3 than in Figure 1. . In this case, the storage keys are all the storage keys of real page numbers corresponding to the specified virtual page number and whose size is determined by the configuration of the hardware. Writing or reading of information will be recorded in the memory key of page 4.

Above, we have described an address translation control method that can arbitrarily change the page size during address translation in a system that employs virtual memory according to the present invention. In this case, almost no modification or increase in hardware is required other than adding a simple switching circuit.

As a result, the present invention improves system economy, stability,
It is possible to improve the efficiency of address translation without impairing reliability, maintainability, etc.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional address translation method in which the page size during address translation is fixed to the minimum unit size determined from the hardware configuration. FIG. 2 is a diagram showing the process of updating the TLB page size.
FIG. 3 is a block diagram when address translation is performed using a TLB whose page size has been updated. 1... Virtual address, 2, 2'... Mark indicating the boundary between the bit width of the virtual page number and the bit width of the address within the page, 3.
・・Signal indicating virtual page number, 4...TLB, 5...Ba-
6... Signal indicating real page number, 7... Real address, 8... Address conversion table, 9... Real page number bit width, 10... Address in page 11... Signal of real page number of the same size as the virtual page, 12... Signal of real page of page of size determined by hardware configuration, 13... Signal of virtual page number A signal indicating the page number,
14...Virtual page number signal with addition of upper 2 bits of intra-page address. Figure 2, Foundation Figure 3

Claims (1)

[Claims] 1 Virtual address and real address translation pairs are transferred to a high-speed element (TL
B) In the address translation control method for an information processing system that performs high-speed address translation, the size is 2^n (n: natural number) times the size of the minimum unit page determined from the hardware configuration. When accessing with a virtual address having a page size, if no address translation pair is registered in the TLB, the address translation table on the main memory is accessed using the page size, and the address translation table is accessed using the page size. The address translation control system is characterized in that the registration in the TLB is performed using a real page number obtained by adding the upper n bits of the intra-page address of the virtual address to the bit width of the real page number obtained from the address translation table.