JPS6024589B2 - Method for manufacturing complementary insulated gate field effect transistors - Google Patents

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a complementary insulated gate field effect transistor (C
The present invention relates to a method for manufacturing a CMOS transistor (MOS transistor), particularly a CMOS transistor using aluminum as a gate electrode material.

[Technical background of the invention and its problems]

There are two main manufacturing methods for CMOS transistors.

FIG. 1 shows an example of one of the manufacturing methods.

According to the manufacturing method shown in FIG. 1, first, as shown in FIG. 1A, the N-type semiconductor substrate 10 is oxidized at high temperature, and the insulating film
form.

Next, a barrier hole is formed by photolithography in a portion where an N-channel transistor is to be formed. Then, a P-type impurity is diffused from here to form a barrier region (p-well) 12. Next, in the step shown in Figure B, a mask material 13 is applied over the entire surface, and a predetermined portion of the mask material 13 is etched away to form a barrier hole. Next, the N-type impurity is diffused from this barrier, and the N-type impurity is
The source region 14, drain region 15 and N+ stopper 16 of the channel transistor are formed at the same time. Next, in the step shown in Figure C, a mask material 17 is applied to the entire surface, and predetermined portions of the mask material 17 are etched away to form barrier holes.

Next, P-type impurities are diffused from this barrier hole to form the source region 18, drain region 19 and ? A stopper 20 is formed at the same time. Next, in a step shown in FIG. 2D, the insulating film 11 and mask materials 13 and 17 are etched away at locations corresponding to the gate portions of the P-channel transistor and the N-channel transistor.

Next, the substrate 10 is oxidized again at high temperature to form thin, uniform gate oxide films 21 and 22. Next, in the step shown in FIG. 5E, mask material 13,
17 is removed by etching, and Sekiguchi 23, 24, 25,
Form 26.

Next, by depositing aluminum or the like on the entire surface of the base and selectively removing the aluminum, the wirings 27 and 28 are
, 29 and gate electrodes 30, 31 are formed, and the CMOS transistor is completed. However, such a manufacturing method has the disadvantage that the photolithography process must be performed many times, which makes the entire manufacturing process complicated.

Furthermore, considering the mask misalignment between photo-etching masks in each photo-etching process, it is necessary to provide overlap and spacing margins for each pattern to account for mask misalignment, which becomes an obstacle to improving the degree of integration of CMOS transistors. There was also a drawback. Other manufacturing methods to eliminate such drawbacks include Japanese Patent Application Laid-Open No. 48-15479 and Japanese Patent Application Publication No. 49-17
Manufacturing methods such as those disclosed in the Wazawa Publication and the like have been proposed. In this method, first, a gate insulating film and a gate electrode material are formed and deposited on the entire surface of a semiconductor substrate in which a barrier region is formed, and this two-layer structure is coated with a P channel using a single mask. The gate portion of the N-channel transistor is removed by etching.

Next, using the gate portions of the remaining P-channel transistors and N-channel transistors as masks, the respective sources and drains are formed by impurity diffusion, and then,
The CMOS transistor is completed by making the desired wiring. According to this method, the number of photo-etching steps can be reduced compared to the first manufacturing method described above, the entire manufacturing process can be simplified, and mask misalignment between each photo-etching mask can be reduced. The resulting obstacles to increasing the degree of integration can also be improved.

However, this manufacturing method had the following drawbacks.

In other words, since the gate part of a CMOS transistor is used as a diffusion mask when forming the source and drain, impurities for source and drain diffusion are also diffused into the gate electrode and gate insulating film that constitute the gate part. I end up.

As a result, in the completed CMOS transistor,
As a result, the voltage value fluctuates and the withstand voltage of the gate insulating film decreases. Furthermore, when this manufacturing method is applied to an aluminum gate type CMOS transistor, there is a drawback that diffusion conditions such as diffusion temperature and diffusion time during source and drain diffusion are limited due to the low melting point of aluminum, which is the gate electrode material. Ta.

[Purpose of the invention]

The present invention was invented in order to eliminate the drawbacks of the conventional method for manufacturing aluminum gate type CMOS transistors as described above, and its purpose is to reduce the threshold voltage, the fluctuation of the value voltage, and the withstand voltage of the gate insulating film. The diffusion conditions during source and drain diffusion are not limited by the low melting point of aluminum, and the manufacturing process is simple, eliminating obstacles to increasing the integration density caused by mask misalignment between photolithography masks. An object of the present invention is to provide an improved method of manufacturing a CMOS transistor.

[Summary of the invention]

The present invention involves the step of providing a sheet of mask material on a substrate and well, and the portions of this mask material where P-type and N-type impurities are to be diffused, such as the sources and drains of P-channel transistors and N-channel transistors. In the place corresponding to
The process of providing a Sekiguchi at one time and the P-type (
A P-type solid-phase diffusion source is provided at a location corresponding to the area where OUTDIFFUSI (N-type) is to be diffused.
A step of providing an ON prevention film, a step of heating this substrate in an N-type (P-type) atmosphere to simultaneously diffuse P and N, and the above-mentioned mask material, solid phase diffusion source, and OUTDIFFUSIO.
This method consists of a step of removing the N prevention film and a step of forming a gate insulating film, an aluminum gate electrode, a wiring electrode, etc. in predetermined portions, thereby solving various problems of the prior art.

[Embodiments of the Invention] Hereinafter, the present invention will be explained in detail by way of embodiments with reference to the drawings.

FIG. 2 is a manufacturing process diagram showing one embodiment of the present invention.

First, in the step shown in FIG. 2A, the substrate concentration is about 1 to 5.
An N-type semiconductor substrate 100 having shapes 1 and 7 [arc-3] is prepared. Then, this base body 100 is oxidized at high temperature to form an insulating film 1.
form 10. Next, in this insulating film 110, N
A barrier hole is formed by photolithography in a portion where a channel transistor is to be formed. Next, from this checkpoint, B203
, 1 and 6 to 1 and 7 by diffusing impurities that give P type such as BN.
Barrier region with a concentration of about [enemy-3] (P1 Book II)
120 is formed. Next, in the step shown in FIG.
00 is oxidized at high temperature to form an insulating film (first insulating film) 130 over the entire surface of the base 100. Note that this insulating film 130' serves as a mask for diffusing the source and drain, so it must be a mask that does not allow conductive impurities for diffusion to pass through. Next, in this insulating film 130, a source 140 of an N-channel transistor, which will be explained later using FIG.
, the drain 150 and the N+ stopper 160, and the source 170, drain 180 and P+ stopper 190 of the P channel transistor are formed at a time by photolithography using one mask. A first diffusion window and a second diffusion window) are formed. Next, in the step shown in FIG. 2C, an insulating film containing N-type impurities, such as glass containing phosphorus (hereinafter referred to as PSG film) (second insulating film) 200, is deposited on the substrate 10 after the above step. .

Next, a CVD film (third insulating film) 210 is laminated on this PSG film 200. Note that this CVD film 210 is used as the OUTDIFF from the Kamo G film 200 during the heating process described later.
For purposes such as preventing USION, it must be impermeable to conductive impurities for diffusion. (Hereinafter, the laminated film consisting of the PSG film 200 and the CVD film 210 will be collectively referred to as a low-temperature oxide film.) Next, in the step shown in the figure ○, the source 170 of the P-channel transistor, the source 170 of the P-channel transistor,
The area above and around the opening (first diffusion window) corresponding to the drain 180 and P+ stopper 190 is removed by photolithography.

This low-temperature oxide film is an insulating film 1 formed by high-temperature oxidation.
Compared to 30, the etching speed is several times to ten times faster, so insulating film 1
Over-etching to 30 is negligible. Next, the substrate 100 is placed in a diffusion furnace according to a conventional method and heated to form a target.
Phosphorus is solid phase diffused through the openings from the membrane 200 to form the source 140, drain 150, and N stopper 160 of the N-channel transistor, and BN or phosphorus is diffused through the other openings.
P-type impurities are vapor-phase diffused in an atmosphere such as No. 3 to simultaneously form the source 170, drain 180, and P-stopper 190 of the P-channel transistor. Next, in the step shown in FIG.
10 is removed by photolithography.

Next, the substrate 100 is oxidized again at high temperature to form thin and uniform gate oxide films 220 and 230. Next, gate oxide films 220 and 2 are formed to wire the sources and drains of the P-channel transistor and the N-channel transistor.
30 sources, drains 140, 150, 170, 18
The portion corresponding to 0 is removed by etching, and the closed openings 240, 250,
260 and 270 are formed. Next, aluminum is vacuum-deposited over the entire surface of the base 100. Next, aluminum is selectively removed by photolithography to form drain region 1.
A conductor 280 connecting between 50 and 160, a low potential power supply (
) and the source 140 of the N-channel transistor, a gate electrode 300 of the N-channel transistor, and a gate electrode 3 of the P-channel transistor.
10. Form a conductor 320 connecting a high potential power source (not shown) and the source of the P-channel transistor. As a result, an inverter circuit using aluminum gate type CMOS transistors is completed. [Effects of the Invention] According to the present invention, since there is no impurity diffusion into the gate part of the transistor, there are no problems such as fluctuations in threshold voltage or a decrease in the withstand voltage of the gate insulating film. Because of this, the diffusion conditions during source and drain diffusion are not limited by the low melting point of aluminum, and moreover, it is a CMOS with improved integration density caused by mask misalignment between each photolithography mask. A method for manufacturing a transistor could be provided.

[Brief explanation of drawings]

1A to 1E are diagrams of a conventional acid forming process for a CMOS transistor, and FIGS. 2A to 2E are diagrams of a manufacturing process of a CMOS transistor according to the present invention. 100... Semiconductor base, 110... Insulating film, 1
20... Barrier region, 130... Insulating film (first insulating film), 140... Source of N channel transistor, 150... Drain of N channel transistor, 1
60...N+ stopper, 170...Source of P channel transistor, 180...Drain of P channel transistor, 190...P10 stopper, 200...
...Tower G film (second insulating film), 210...CVD film (third insulating film), 220...N-channel transistor gate oxide film, 230...P-channel Gate oxide film of transistor, 240, 250, 260, 27
0... Sekiguchi, 280, 290, 230... Conductor (wiring electrode), 300... Gate electrode of N channel transistor, 310... Gate electrode of P channel transistor . Figure 1 Figure 2

Claims (1)

[Claims] 1. Forming a first insulating film that does not allow diffusion conductivity type impurities to pass through on a semiconductor substrate having a first region of one conductivity type and a second region of the other conductivity type on the surface;
A first diffusion window corresponding to the source and drain of the first MOS transistor formed in the first region, and a second diffusion window corresponding to the source and drain of the second MOS transistor formed in the second region, forming the first insulating film using one mask;
forming a second insulating film containing a first conductivity type impurity on the second diffusion window and on the first insulating film; a step of forming a third insulating film on the first diffusion window; a step of removing the third insulating film on the first diffusion window; using the third insulating film as a mask, removing the second insulating film; exposing a diffusion window; vapor-diffusing a second conductivity type impurity into the first region through the first diffusion window;
While forming the source and drain of the S transistor, a first conductivity type impurity is solid-phase diffused from the second insulating film into the second region through the second diffusion window, and
a step of forming a source and a drain of an OS transistor; a step of removing the first, second, and third insulating films;
Subsequently, forming gate insulating films of the first MOS transistor and the second MOS transistor at predetermined portions on the first region and the second region, respectively; Next, on the gate insulating film and the predetermined regions, 1. A method for manufacturing a complementary insulated gate field effect transistor, comprising the steps of forming a gate electrode and a wiring electrode made of aluminum, respectively.