JPS6024670B2 - Inverter control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control circuit for an inverter (hereinafter abbreviated as a PWM inverter) that modulates the pulse width of an output waveform at a frequency higher than the fundamental frequency, and particularly to a control circuit for a current source PWM inverter.

FIG. 1 shows a main circuit of a series diode type three-phase bridge current source inverter as an example of an inverter main circuit to which the present invention can be applied.

In FIG. 1, 1 is a current-controllable DC power supply, 2 is a DC reactor connected in series with the DC power supply 1, 3 is a current source inverter main circuit, and 4 is an AC motor having terminals U, V, and W. The current source inverter main circuit 3 includes six thyristors 11 to 16 and six series diodes 21 to 26.
, six commutation capacitors 31 to 36.
Using the current type inverter shown in Fig. 1,
Each thyristor 1 when performing energized inverter operation
FIG. 2 shows gate signal waveforms GI to G6 and output current waveforms IU, lv, and lw to be added to signals 1 to 16.

In FIG. 2, GI indicates the gate waveform of the thyristor 11, and G2, G3, G4, G5, and G6 similarly indicate the gate waveforms of the thyristors 12, 13, 14, 15, and 16. Also, IU, lv, and lw are D and V of the AC motor, respectively.
, W shows the current waveform (inverter output current waveform) flowing through each terminal. Since the operation of the 12-pin current source inverter is already well known, detailed description thereof will be omitted.

Next, a case will be described in which the current source inverter is operated as a current source PWM inverter without performing the 120° energization operation.

FIG. 3 shows gate signal waveforms GI to G6 and inverter output current waveforms 1u, lv, lw for PWM controlling the current source inverter. FIG. 3 corresponds to one period (conducting angle of 360 degrees) of a current source PWM inverter. Of these, focusing on the gate signal waveform GI given to the thyristor 11, the gate signal is always given during the energization period oo to 600, and the thyristor 11 and the thyristor 13 are alternately turned on and off during the energization period 60o to 1200. period (hereinafter referred to as PWM period)
3), the energization period from 1200 to 3000 is always off, and the energization period from 3000 to 3600 is the P by thyristor 15 and Cy IJ star 1.
The WM period is P5. The same process is performed for the remaining five gate signal waveforms G2 to G6 with a phase difference of 60 degrees. Regarding the PWM period in which thyristors other than thyristor 11 are involved, as shown in FIG.
35, P24, P46, P group. The current waveform obtained as the inverter output by these gate signals is IU
, lv, lw. Three current waveforms lu, lv
, lw are applied to the U, V, and W terminals of the AC motor 4 as three-phase alternating currents having a phase difference of 1200 degrees.

The early non-WM period in which the two thyristors alternately turn on and off is detailed as follows, taking P,3 as an example.

That is, the thyristor 11 continues to be turned on for a further period Q after the period from oo to 60o in which the gate signal is always applied is completed. After this, the thyristor 11 is turned off for the energization angle Q2, and the thyristor 13 is turned on for the same period. Next, the thyristor 11 is turned on and the thyristor 13 is turned off for the same conduction angle Q2. Finally, thyristor 1
1 is turned off and the period in which the thyristor 13 is turned on continues for Q, and then the PWM period P,3 ends. Gate signal waveform G
Focusing on one cycle of I (conducting angle 360 degrees), the period during which the on signal is given is 6 and 12 (Q, 10 Q2) = 12, which is the same as when energizing 1200 times as shown in FIG.

In other words, the ON period of 12 pins is not given continuously, and the PWM
Any period Q2 among the conduction angles 30o at both ends, which is the period
are placed in a separated state. Therefore, although Q2 is arbitrary, it is necessary to satisfy the following condition: 2<300.

Also, three phases involved in PWM (in this case U phase and V phase)
In order to make the current waveforms the same, it is necessary that the gate signal of the separated period Q2 is separated from the original gate signal by the period Q2, and this Q2 interval is the same as that of the other phase. period. That is, periods Q1 and Q2 are PWM period 6.
It is necessary to arrange them symmetrically with respect to the central point 300 of 0o. The same applies to other PWM periods. In FIG. 3, a case has been described in which one separated pulse with a conduction angle Q2 is generated during the PWM period with a conduction angle of 60o, but the same holds true when two or more pulses are generated. FIG. 4 shows the gate signal waveform when the number of pulses to be separated is changed by performing PWM operation.

GIO is a gate signal waveform during normal 120° current conduction operation without PWM operation. GII is the gate signal waveform when the pulses are separated one by one before and after the energization period Q2 from the 120o energization period. GI2, GI3
, GI4 are gate signal waveforms when two, three, and four pulses are separated, respectively. Moreover, FIG. 5 shows the output current waveforms of the inverter operated by the gate signals shown in FIG. 4, 1, o, 1, . ,112,113,11
4 are gate signal waveforms GI0, GI1, GI2, respectively.
This is the output current waveform of the inverter operated by GI3 and GI4. Considering the case where N pulses are generally separated, the conditions required for the gate signal waveform during the PWM period are summarized as follows. (1) In the PWM period 600, the conduction angle Q is arranged symmetrically with respect to the 300th point in the PWM period. (In other words, when N pulses are separated during the PWM period, Q,,〇2,〇3...Qn,〇n11,Qn1,'〇n,...Q3,Q2,Q, The PWM period is divided into Q, 10Q2 10Q3...10Qn+QM=300.
) (0) On and off are alternately repeated during the divided periods. Further, the on and off relationships in the gate signals of the two thyristors during the PWM period are completely reversed. The above are the characteristics when PWM operation is performed by a radio waveform inverter with 1200 energization, and clearly under the above two conditions, the far field angle is 1200 when the on-periods are totaled regardless of the number of separated pulses.

Also, the six gate signals GI to G6 have the same waveform, and 3
The phase output currents IU, lv, and lw also have equal and symmetrical waveforms. The output current of a radio waveform inverter running at 120o contains the following harmonic components (Setsuji 1), but PWM
The conduction angle Q. It is known that the high frequency components contained in the output current can be reduced by appropriately determining .

For this reason, performing PWM operation with a current source inverter is effective in reducing torque ripple, especially when the inverter output frequency is low.

At this time, if Q,, Q2...Qn are selected such that the average value of the inverter output currents IU, lv, lw can be approximated to the trapezoidal wave shown by the broken line in Fig. 5, a good signal with few high frequency components can be obtained. It is also known that current waveforms can be obtained. For this purpose, it is necessary to determine Q, Q2, . . . qn such that the gate signal waveform can be approximated to the trapezoidal wave shown by the broken line in FIG. A common gate signal synthesis method for a PWM inverter is to compare a carrier wave C and a reference wave R.

An example of the prior art is shown in FIG. A comparator 106 compares a carrier wave C with a constant frequency higher than the inverter fundamental frequency obtained from the oscillator 100 and a reference wave R synchronized with the inverter fundamental frequency obtained from the counter 10S to obtain a gate signal G. It is unsuitable for use in generating a gate signal for a type PWM inverter.Since there is no correlation between the carrier wave and the reference wave, the two conditions required for the gate signal waveform cannot be satisfied.As a result, 6
The two gate signal waveforms are different from each other, and the motor phase currents are asymmetrical. In other words, in a state where there is no relationship between the carrier wave C and the reference wave R, it is clear that it is difficult to arrange the conduction angles Q during the PWM period symmetrically and to set the total on period to 1200. . Another example of the prior art is shown in FIG. Carrier wave C having a frequency n·na that is an integral multiple of the inverter fundamental frequency n obtained from the counter 104
A comparator 106 compares the reference wave R synchronized with the inverter fundamental frequency obtained from the counter 105 to obtain the gate signal G. In this case, since there is always a frequency difference of an integral number n times between the carrier wave C and the reference wave R, the conduction angle Q during the PWM period can be kept constant regardless of the magnitude of the inverter frequency. However, condition 1 of the two conditions required for the gate signal waveform cannot always be satisfied.In other words, there is no guarantee that the conduction angle Q will be symmetrical with respect to the center point 300 o of the PWM period 60 o. Since the frequency of C is proportional to the inverter fundamental frequency, the modulation frequency of the PWM waveform fluctuates greatly. The purpose of step 1 is to create a current shape PW that can maintain the same current waveform for each phase of the motor.
The second object is to provide a control circuit for an inverter, the second object is to provide a control circuit capable of synthesizing a conduction angle Q such that a PWM waveform can be approximated to a trapezoidal wave, and the third object is to reduce the inverter fundamental frequency. An object of the present invention is to provide an inverter control circuit in which the modulation frequency of a PWM waveform (the modulation frequency of a carrier wave C) is constant regardless of changes in the carrier wave C.

An embodiment of the present invention shown in FIG. 8 will be described below.

Here, m, n, and n are all integers. A signal ahn with a frequency 6・m・n times the inverter fundamental frequency n
, and outputs a signal 8h with a frequency of 1/n, and a frequency divider 102 that outputs 6 signals with a frequency of 1/m are connected in series. Connect to. The selection circuit IQ3 selects and outputs a signal pattern having an arbitrary frequency division ratio in the frequency dividing circuit 101. The signal 8hn'' becomes an input to the counter 104, and the counter 0
4 outputs a carrier wave C having a chain tooth waveform with a height of m and a frequency node. Another counter 105 receives the signal level hna as an input and outputs a reference wave R having a lock-tooth waveform with a height m and a frequency of 6''.A comparator receives the carrier wave C and the reference wave R as input. 106 compares both signals and outputs a magnitude determination signal D. Furthermore, a hexadecimal ring counter 1
07 inputs the signal 6na and outputs 6 signals RCI to RC.
Outputs 6. A waveform synthesis circuit 108 which receives the six signals RCI to RC6 and the large 4 discrimination signal D synthesizes gate signals GI to G6 of each thyristor from these signals. Finally, the frequency division ratio selection signal S is selected from the selection circuit 103 by the frequency detection circuit 109 which inputs the signal 6mnna.
Add to. Next, the operation of the control circuit of the present invention constructed as described above will be explained using FIG. 9 as an example where n=4.

The reference signal for the inverter fundamental frequency fundamental frequency is calculated from various information such as motor rotation speed and rotation command, and then
The signal 8rn having a frequency of hn is input to the control circuit of the present invention. Since the arithmetic processing circuit has no direct relation to the present invention, a description thereof will be omitted. Signal storm hn. 〆Frequency divider circuit 1
The frequency is divided into 1/mount by 01. In other words, the frequency dividing circuit 101
The output of is the signal trace na. The division ratio is selected by selecting an arbitrary signal from among various frequency signals (for example, mother m mountain na, 8hn3 na, etc., however, n,〉~>touch〉...ZI) inside this frequency dividing circuit 101. The function of the selection circuit 103 is to select based on the signal S. The counter 104 is the selection circuit 10
The output signal 8hn〆 of 3 is input.

Since the counter 04 is set in advance to be set when the output reaches m, a mirror-tooth waveform with a height m is obtained as the output. This frequency becomes a node. In other words, a number of mirror-tooth waves are included in one period of the inverter fundamental frequency. (N chain-tooth waves enter the conduction angle 6.) Changing n by the selection circuit 103 means that the conduction angle 600
This will change the number of mirror tooth waves that enter. This sawtooth wave is used as a carrier wave C and is input to one side of the comparator 106. Next, another counter 105 to which the signal level is inputted is also set to set IJ when the output reaches m, like the other counter 104. Therefore,
A mirror-tooth waveform with a height of m and a frequency of 6 na is obtained as an output.
One mirror-tooth wave always enters the conduction angle 600. ) This sawtooth wave is used as the reference wave R and the other input of the comparator 106. A comparator 106 compares the carrier wave C and the reference wave R and outputs a magnitude determination signal D. At this time n
Regardless of the value of , the conduction angle of carrier wave C and reference wave R is 600.
Since the two conditions intersect at the center 300 of the gate signal waveform, the two conditions required for the gate signal waveform are satisfied. Another frequency dividing circuit 102 receives the predetermined 8h as input and divides the frequency into 1/m. In other words, the output signal is 6 na. hexadecimal ring counter 1
07 inputs this signal 6na and outputs 60o ON signals RCI to RC6 having a phase difference of 60o.

These signals RCI to RC6 function as distribution signals for distributing gate signals to six thyristors 11 to 16. The waveform synthesis circuit 108 synthesizes the signals RCI to RC6 and the magnitude discrimination signal D to generate six gate signals GI to G6.
make. The 6-bit period that must be turned on (for the gate signal G6 in FIG. 9, the period from 600 to 1200)
This is determined by the six on-periods (RC6 in the above case) of the hexadecimal ring counter output. P of 60o before this period
During the WM period (period from oo to 600), the magnitude determination signal D directly becomes the gate signal G6. In the subsequent PWM period of 60o (period from 120o to 180o), the negation of the magnitude discrimination signal D becomes the gate signal G6. By synthesizing the waveforms in this way, it is possible to create a gate signal waveform that is symmetrical in front and back. Further, the frequency detection circuit 109 outputs a frequency division ratio selection signal S to select n which is inversely proportional to the inverter fundamental frequency. This is done in order to keep the modulation frequency constant by setting n in an inversely proportional relationship since the frequency of the carrier wave C is a regular n. As explained by Father L, the present invention has the following effects. {a- Since the carrier wave and the reference wave are always made to intersect at the center of the conduction angle 60o, the current waveforms of each phase can be maintained equally even when PWM operation is performed.

{b' By detecting the inverter fundamental frequency and controlling the frequency ratio between the carrier wave and the reference wave by changing it, the frequency of the carrier wave and the modulation frequency can be maintained constant.

[Brief explanation of the drawing]

Fig. 1 is a main circuit configuration diagram showing an embodiment of a current source inverter to which the present invention can be applied, and Fig. 2 is a gate signal waveform and phase of the current source inverter shown in Fig. 1 when performing a conventional 1200 current conduction operation. Current waveform diagram, Figure 3 is a gate signal waveform and phase current waveform diagram to explain the operation when the current source inverter in Figure 1 is pulse width controlled, and Figure 4 is a diagram of the pulses separated by pulse width control. Figure 5 is a phase current waveform diagram obtained by operating the current waveform inverter using the gate signal in Figure 4. Figures 6 and 7 are conventional waveform diagrams. FIG. 8 is a diagram for explaining the operation when the pulse width is controlled by the control circuit of FIG. FIG. 9 is an operational waveform diagram of each part in the control circuit for explaining the operation of FIG. 8. 101, 102... Frequency dividing circuit, 103...
...Selection circuit, 104,105...Counter,
106... Comparator, 107... Hexadecimal ring counter, 108... Waveform synthesis circuit, 109...
...Frequency detection circuit, 8hn, na...6.m.n, double signal of inverter fundamental frequency, 5 h ratio...
Inverter fundamental frequency multiplied by 6.m.multiple signal, 8hn3... Inverter fundamental frequency multiplied by 6.m.w signal, 8hn
N... Signal 6・m・n times the inverter basic frequency, 8h〆...・・6・m of infrared fundamental frequency
Double signal, 6 signals...Six times the inverter fundamental frequency, C...Carrier wave, R...Reference wave, D...
...Size discrimination signal, RCI to RC6...
Hexadecimal ring counter output signal, GI to G6...gate signal of thyristors TI to T6, S...dividing ratio selection signal. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9

Claims (1)

[Claims] 1 In an inverter that modulates the pulse width of the output waveform at a frequency higher than the inverter fundamental frequency, 6・m・n1 times the inverter frequency f (m and n1 are integers)
Inputting a signal 6mn1f with a frequency of 1/n1
a first frequency dividing circuit that outputs a signal 6mf having a frequency of 1/m; a second frequency dividing circuit that receives the output 6mf of the first frequency dividing circuit and outputs a signal 6f having a frequency of 1/m; The output 6f of this second frequency dividing circuit is input and six signals RC
a hexadecimal ring counter that outputs 1 to RC6;
a frequency detection circuit that inputs 6mn1f input to the frequency divider circuit and outputs a frequency division ratio selection signal S; and a frequency detection circuit that receives the signal output from the first frequency divider circuit and outputs the frequency division ratio selection signal S. A selection circuit that selects and outputs a signal 6mnf having an arbitrary frequency division ratio according to a frequency division ratio selection signal S, and a selection circuit that inputs the output 6mnf of this selection circuit and outputs a signal 6mnf with a height m and a frequency 6.
A first counter outputs a carrier wave C having a sawtooth waveform of nf, and a reference wave R having a sawtooth waveform of height m and frequency 6f by inputting the output 6mf of the first frequency dividing circuit. a comparator that inputs the carrier wave output from the first counter and the reference wave R output from the second counter, compares these two signals, and outputs a magnitude discrimination signal D; The six signals RC1 to RC6 output from the forward ring counter and the magnitude discrimination signal D output from the comparator are input, and these signals are distributed and combined to generate a gate control signal G to each electric valve of the inverter.
An inverter control circuit comprising a waveform synthesis circuit that outputs signals G1 to G6.