JPS6024972B2 - Signal transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for transferring digital signals that are continuously sent out from a sending device on a daily basis when transferring signals between devices that have different internal signal processing speeds. , some parts are transferred directly to the receiving device, while other parts are transferred through a constant storage device, which converts the bit order and bit spacing, and is transmitted continuously at low speeds in low-speed devices. , in high-speed devices, involves a method that enables intermittent high-speed signal processing.

Hereinafter, in particular, the central processing unit (abbreviated as CPU) of an electronic computer
A detailed explanation will be given by taking an example of signal transfer between a magnetic disk drive and a magnetic disk device serving as an external auxiliary storage device.

Note that it is the so-called input/output control device that directly exchanges signals with the magnetic disk device, but in this specification, the C
Considering the functions of PU, magnetic disk device and CP
It is assumed that U directly receives and transfers signals. Conditions for improving the performance of electronic computer systems include increasing storage capacity and increasing processing speed (including access speed).

This directly applies to magnetic disk devices that are external auxiliary storage devices.

In order to increase the storage capacity of a magnetic disk device, it is necessary to increase the number of tracks on one disk and the linear density of information within one track.

By the way, when increasing the linear density of information information in one track, that is, the number of bits per unit length, in order to increase the storage capacity as a magnetic disk blind pupil, it is necessary to reduce the rotation speed of the disk, or The read/write frequency in the read/write head must be increased.

However, lowering the disk rotation speed is undesirable because it increases access time.

Therefore, it is necessary to increase the write frequency.

Currently, this frequency (speed) has been increased to the same level as the processing speed inside the CPU.

By the way, the CPU has input/output devices other than magnetic disk devices,
For example, card readers, line printers, magnetic tape devices, etc. are also connected, but the processing speed of these devices is C
It is normal that the processing speed is considerably slower than that of the PU. Therefore, the input/output control section of the CPU is provided with a buffer memory so as to receive and receive signals in parallel and in a time-division manner to a plurality of input/output devices having slow processing speeds.

In such a case, if a magnetic disk device that is very fast compared to these input/output devices is connected in the same way, the buffer memory of the CPU's input/output control unit will be occupied by the magnetic disk device and the speed will be reduced. input/output devices become uninterruptible.

Therefore, it is necessary to newly provide a buffer memory for high-speed devices separately from a buffer memory for low-speed devices.

In such a case, the present invention allows signals to be transferred at low speed from the CPU's perspective, similar to those for conventional low-speed devices, and inside the magnetic disk device, signals can be transferred to the magnetic disk at high speed. The purpose of the present invention is to provide a transfer method that enables writing and reading of signals, and thus substantially increasing storage capacity.

Conventionally, when converting transfer speeds like this, it is common to memorize a group of signal strings one by one, and then read them out later at a different speed than when they were stored.In this method, the lower speed signals are continuously In order to do this, it is necessary to provide two storage devices and write and read data sequentially and alternately, but with the present invention, this is possible with one storage device.
This allows efficient speed conversion. Specific examples will be described in detail below. Now, let us consider the case where a serial signal sent from the CPU at a transfer rate of 4 megabits/second is received, and the magnetic disk device writes to the disk at a writing speed of 8 megabits/second. It is assumed that the magnetic disk drive is equipped with a buffer memory with a capacity of 1100 bits, and the signals continuously transferred from the CPU are also divided into 1100 bits, which will be referred to as one block.

According to the present invention, of the continuous signals transferred from the CPU, the entire first block is stored in one buffer memory, and then the next block is stored.

The bits of the first block are alternately inserted between the bits of the first block and sent to the write head.
At this time, the present invention is characterized in that each bit of the second block uses the transfer signal from the CPU as it is.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is an explanatory diagram during the write operation described above.
In the figure, CPU is a central processing unit (including an input/output control device), SW is a changeover switch, BAIEM is a buffer memory, DLY is a delay circuit, ORG is an OR gate, AMP is a multiplier, and HEAD is a write head. Also, Fig. 2 is a diagram explaining bit order conversion, and Fig. 2 a shows the CPU
The first block is A, the second block is B, and AI to AIlO0, respectively.
and 1100 bits BI to BIIOO.

Further, b in the figure shows the bit order of the converted signal output from the OR gate ORG.

In the figure, the inside of each bit (or bit interval) is a, b
Although both are drawn in the same way, the bit interval in Figure a is actually 250 nanoseconds, and the bit interval in Figure b is 125 nanoseconds.

This is natural since the transfer rate from the CPU is 4 megabits/second and the writing speed to the disk is 8 megabits/second. In FIG. 1, the switch SW is initially closed to the buffer memory BMEM side, and the first block A
remember everything.

At this time, the storage speed is of course 4 megabits/second. When the buffer memory BM old M is full, the switch SW closes to the delay circuit DLY side, and the first bit B-1 of the block B is
is input to DLY. At the same time, buffer memory BME
The stored first bit AI of block A is output from M.

Here, if the delay time of the delay circuit DLY is 125 nanoseconds, bit A-1 first appears at the output of the OR gate ORG, and then, 125 nanoseconds later, bit B from DLY appears.
-1 appears.

Then another 125 nanoseconds later, bit B-1 becomes D
250 nanoseconds after being input to LY, the next bit B-2 from the CPU is input to DLY via switch SW, and at the same time bit A-2 is output from buffer memory BMEM as before. Bit A-2 appears as is at the output of OR gate ORG, and 125 nanoseconds later bit B-2 from DLY appears.

Similarly, the bit order of the output of the OR gate ORG is converted as shown in FIG. 2b, and the bit interval is shortened to 250 nanoseconds.

The conversion operation is performed in exactly the same manner for the third and fourth blocks.

In this way, two blocks become a unit for one conversion operation, but this is a problem only in the above-mentioned conversion operation within a magnetic disk drive, and from the CPU's perspective, there is no signal at all. There is no need to be aware of the boundaries.

This is a portion of the signal from the CPU (in this example, the second block).

Even-numbered blocks such as block B) are directly connected to the OR gate O without going through a storage device (through the delay circuit DLY, but this is not an essential element for the present invention).
This is because the signal is input to the RG, and this is the greatest feature of the present invention. By the way, as a result of speed conversion in this way, on the high speed side, that is, on the write head HEAD, the speed is 2.
However, since the signal becomes intermittent, some effort is required to allocate the writing position on the magnetic disk.

The rotation of a magnetic disk cannot be stopped for each block, unlike the tape running in a magnetic tape device.

Therefore, it is necessary to make the writing position on the disk surface irregular.

FIG. 3 is an example of a method of allocating write positions on the disk surface (referred to as data format). The disk surface is divided into 64 fan-shaped parts (referred to as sectors) divided at equal intervals, and at the same time divided into four concentric tracks.

(Of course, the actual number of tracks is several hundred). Here, each area (referred to as a small sector) specified by a sector and a track will be numbered.

First, there are 3 sectors from SO to S31 as a set of 2 sectors.
Divide into 2.

Also, the track number is within each sector, which is a set of two sectors.
They will be labeled as TO-T3 and T4-T7 from the outside. Note that drawing all 64 sectors would be extremely complicated, so only a portion is drawn in FIG.

If such a data format is set and the storage capacity of one small sector is set to 2200 bits, very efficient writing and reading can be performed. (Actually, the number of sectors is determined so that one small sector has 2200 bits.) The order of small sectors when writing is performed continuously in such a data format is as follows.

Smo-SITO-S2ro...S3mo-S
31T0 (the above corresponds to one track in a normal speed magnetic disk drive). Next, move on to the second track, S
OTI-SITI-S2rl...S30rl-S3
Proceed with 1TI.

, Similarly, the third and fourth tracks, ie, SOT2 to S3
Once all tracks 1T2 and S0r3 to S31T3 have been written, the next track is written to the fifth track, ie, Sm4 to S31T4. (This corresponds to the first track of the second disk in a normal speed disk device.) Thereafter, S5 to S31T5, SOT6 to S31T6, and TOT7 to S31T7 are written in the same manner.

In other words, when data is written at twice the normal speed as in this embodiment, one disk has the capacity of two disks in a normal speed disk device.

Alternatively, it can be said that the number of tracks on one disc is doubled.

Next, a description will be given of the operation when reading a signal written by converting the bit order in this manner.

When reading, one small sector (2 blocks = 2200 bits) is treated as one unit. First, among the signals sequentially read out at 8 megabits/second, the odd numbered bits are directly output, but the even numbered bits are stored in a single buffer memory. Then, the last odd-numbered bit, that is, the 2199th bit, is output as is, and then the last even-numbered bit, that is, the 220th bit, is sent to the buffer memory, and then the stored even-numbered bit is It outputs at a speed of 4 megabits/second. Fourth
The figure is an explanatory diagram during a read operation.

In the figure, HEAD is a read head, AMP is an intensifier, SW is a changeover switch, BMEM is a buffer memory, O
RG is an or gate.

The switch SW is switched for each bit read from the read head HEAD, and the odd numbered bits are directly connected to the OR gate ORO, and the even numbered bits are connected to the buffer memory B.
Sent to MEM.

Then, from the buffer memory BMEM to 125 nanometers,
Every 250 bits/second (ie, at a rate of 4 megabits/second), the even bits are extracted and sent to the OR gate ORG in the same order as they were stored.

As a result, if the contents of the small sector read at this time were as shown in Figure 2b, the ORGATE OR
The output of G is restored and output as shown in FIG. 2a.

In the above embodiment, a case was considered in which data is written to and read from a disk at twice the transfer speed from the CPU, but it is generally possible to convert the speed to n times.

FIG. 5 explains the case where the writing speed is increased by n times.

In the figure, M-1 to M-(n-1) are buffer memories,
DLY-2 to DLY-n are delay circuits, and the rest is the same as in Figure 1.If the storage capacity of each buffer memory is m bits, then the unit for one speed conversion operation (in the above example) In other words, 2 blocks = 2200 bits) is n x m
It's a bit.

To explain the operation, a certain transfer speed (A bit/
Of the m×n bit signals sent in seconds),
The first m×(n-1) bits are one-way buffer memory M-
1 to M-(n-1).

Subsequently, the switch SW is switched to the delay circuit DLY-n side from the 11th m×(n-1) bit, and at the same time, one bit is read from each buffer memory M-1 to M-(n-1). and sent to their corresponding delay circuits. Here M
-1, the 1st bit, M-2, the m+1st bit, m-3, the 11th bit, and so on, M-(
The 11th bit of mX(n-2) is simultaneously read from n-1). In addition, the delay time of each delay circuit is DLY-2
1/nA seconds for DLY-3, 2/nA seconds for DLY-3, and n-1/nA seconds for DLY-n.

As a result, the bit period at the output of ORG 0RG becomes 1 seconds, that is, the speed becomes A bits/second. Further, the read operation is shown in FIG.

In the figure, SW is a changeover switch, M-2 to M-n are buffer memories, and the other parts are the same as in FIG. 4. Of the signals sent from the read head HEAD at M bits/second, the first bit is directly sent to the OR gate ORG, the second bit is sent to the memory M-2, and the nth bit is sent to the memory M-n in the same manner. The n11th bit is sent to the OR gate again, the n+2nd bit is sent to M-2, and so on.
distributed by W. And the m×n bit is memory M
1 from memory M-2 1/nA seconds after being stored in -n
Bit by bit is read out at 1/A second intervals and OR gate is executed.
Sent to G. After all the contents of M-2 have been read out, M-3, then M-4, etc. may be read out in the same manner at 1/A second intervals. As a result, the output of the OR gate ORG has a bit interval of 1/A second, that is, a speed of A bits/second.
It will be restored in seconds.

On the other hand, the data format on the disk is almost the same as in the previous example.

The number of sectors should be an integral multiple of n, and on one track (
n-1) The order of small sectors may be taken every other sector. Next, the operation explained in FIG. 1 will be explained using a circuit diagram of a more specific embodiment.

In Figure 7, CL is a clock pulse generator that oscillates at 4MHz in synchronization with the CPU, SR is a 1100-bit shift register used as a buffer memory, and CT is 11
The power counter of the 0G ship counts the clock pulses to the SR, and when it reaches 110, it outputs one pulse and sets the count to “0.”
” to clear.

FF is a flip-flop, and each time there is a pulse from the counter CT, the outputs (2) and (2) are inverted and the gates GI, G2 are switched.

Further, G3 and G4 are gates that are alternately opened and closed according to the clock. Moreover, FIG. 8 is a time chart.

The numbers in the figure indicate the order of bits sent from the CPU. Initially, the FF output is “1” and “0”
”, and the initial value of the counter CT is also “0”. Of the signals transferred from the CPU, the first 1100 bits are stored in the shift register SR while being sequentially shifted from left to right. It is assumed that the input sampling and shifting operations in the SR are performed at the falling edge of the clock pulse.

The 1100th bit is sampled and transferred to shift register SR.
When stored in the leftmost bit of SR, the first stored bit, ie, the first bit, appears in the rightmost bit of SR.

At the same time, the counter CT counts the clock pulses for the 110th stitch and outputs one pulse, so the FF is inverted and the gate G2 is opened.

Therefore, at this time, the second half of the 1100th bit appears in the output of G2, but the clock signal that enters G3 at this time is “
0'', G3 is closed, and conversely, G4 is open, so bit 1 from SR appears at the output of OR gate ORG.After that, by alternately opening and closing G4 and G3, O
A bit string shortened to twice the speed appears in RG.

In this embodiment, there is no equivalent to the delay circuit DLY in FIG. 1, but this is because the shift register SR is 1100
Since it is a bit, at the same time as the 1100th bit from the CPU is stored, the first bit from the CPU that was stored first is output, so there is no need to apply a delay to the gate G2 side. Further, specific examples regarding the read operation from the disk are shown in FIGS. 9 and 10.
In the figure, SR is a 1101-bit shift register,
FFI is a flip-flop for switching the clock phase to SR, FF2 is a flip-flop for sample and hold, CT is a 110-gun counter, and CL is a clock generator of MHZ synchronized with the read signal. First FF
Since the output of I is ``1'' and ``0'', shift registers SR and FF2 receive clocks with opposite phases,
As a result, every other signal output from the amplifier AMP is sampled alternately in SR and FF2. Therefore F
The output of F2 has 250 bits from the 1st bit to the 1100th bit.
Appears at nanosecond intervals. Also, the sample at SR is 110M.
When the count is completed, the counter issues one pulse and the FFI is inverted, so the clock pulse to the SR will be in reverse phase.
At this time, the SR is set to 1101 bits in order to provide a delay of 125 nanoseconds to the output of the SR. In the above embodiment, a shift register was used as the buffer memory, but
In general, any circuit that has a memory function or a delay function can be implemented. Also, most of the elements can be shared between the writing circuit and the reading circuit, but if the two circuits are provided separately, from the CPU's perspective, writing and reading can be done simultaneously using one head. It becomes possible to do so. As detailed above, in the present invention, when performing speed conversion, a part of the signal from the low speed side (or to the low speed side) is output directly to the high speed side (or from the high speed side),
The other parts are stored in a flat buffer memory and then output to the high speed side (or to the low speed side) at an appropriate timing, so that the speed can be continuously increased using one buffer memory when viewed from the low speed side. This provides a signal transfer method that allows conversion.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram at the time of writing in one embodiment of the present invention,
Figure 2 is a diagram explaining the bit order of the signal, Figure 3 is a diagram explaining the data format on the disk, Figure 4 is a diagram explaining reading, and Figures 5 and 6 are general diagrams when the speed conversion ratio is n. FIG. 7 is a specific example of the write circuit, FIG. 8 is a time chart thereof, FIG. 9 is a specific example of the read circuit, and FIG. 10 is a time chart thereof. In FIGS. 1 and 4, CPU is a central processing unit including an input/output control section, BMEM is a buffer memory, ORG is an OR gate, AMP is an intensifier, and HEAD is a head for both writing and reading. In addition, in FIGS. 7 and 9, SR is a shift register, FF, FF1, and FF2 are flip-flops, and CT is a 1
A decimal counter, CL a 4MH2 clock generator, and IV an inverter. Many figures, many 2 figures, many 3 figures, many 4 figures, grandchildren, etc., many 7 figures, many 8 figures, inferior? Figure 0'0

Claims (1)

[Claims] 1 In a method of transferring digital signals between two devices with different internal processing speeds, each bit of the bit sequence of the digital signal sequentially sent from the high-speed device is every (n-1) bits from the first bit. The other bits are transferred directly to the low-speed device (n is an integer of 2 or more), the other bits are temporarily stored in the storage device, and after the transmission from the high-speed device is completed, the stored bit string is transferred to the high-speed device. A signal transfer method characterized in that the transfer speed is reduced to 1/n by sequentially reading data at 1/n of the transmission speed and transmitting the data to a lower speed device.