JPS6025799B2 - Rhythm pattern variation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a rhythm pattern variation device that can easily add musically diverse rhythm patterns without increasing the capacity of a storage device.

Conventional rhythm pattern generators use fixed memory (ROM)
The rhythm patterns of each 4-measure or several-measure rhythm pattern are stored in the memory.

If you try to add variations to this pattern, R
The content of the OM becomes large and the circuit and structure become complex. The basic configuration of a conventional rhythm generator will be explained with reference to FIG.
The address counter 2 is counted by the J rhythm clock, and the rhythm pattern stored in the ROM 3 is set on the line la according to the address signal from the address counter 2.
Output to ~ln. The output of each line opens the gate '1}4, ~(n)4n according to its rhythm pattern,
The sound from each sound source 5, ~5n is output, and the mixer 6
Add these together and output. As will be seen, since rhythms are stored in the ROM 3 or are limited to rhythm patterns only, the storage capacity becomes extremely large as variations become more diverse. An object of the present invention is to provide a rhythm pattern variation device that can easily add musically diverse rhythm patterns without increasing the capacity of a storage device. In order to achieve the above object, the rhythm pattern variation device of the present invention includes an address counter that generates an address signal for reading a memory bag in accordance with a rhythm clock, a storage device that outputs a pre-stored rhythm pattern according to the address signal, and a rhythm pattern that is output from the memory bag. means for branching the rhythm pattern into two lines; a variation circuit for creating an IJ rhythm pattern with a desired time delay from the rhythm pattern on one branched line; and a time delay between the rhythm pattern on the other branched line and the variation circuit. and a circuit for generating a low frequency clock for controlling the means for branching into the two lines and the variation circuit for creating the time-delayed rhythm pattern. .

The present invention will be described in detail below with reference to examples.

FIG. 2 is a basic block diagram showing the configuration of an embodiment of the present invention.

The rhythm clock generator causes the address counter 12 to count, and depending on the address signal from the address counter 12, the rhythm pattern is stored in the ROM 13 or output to lines la to ln. If the gate 14 is closed, the rhythm pattern output to the line la will be guided only from the line 2 through the gate 17 to the sound source 1, that is, only the main rhythm pattern will be extracted. This gate 14 is controlled by line 18 of a low frequency clock generator 20. Next, when the gate 14 opens, the rhythm pattern is branched out along with line 2 to line 3.

The output of this line 3 is split into lines 4 and 5, and the pulses on line 5 enter a select gate 15 controlled by line 19 of the low frequency clock generator 20 mentioned above.
S... Output to one of the lines S2, . . . , Sn. On the other hand, the pulse on line 4 is delayed by the delay circuit 21 and input into the shift register 16 to become a read pulse. Further, the rhythm clock outputted from the rhythm clock generator 11 is branched and applied to the shift register 16 as a shift clock. As the output of this shift register 16, a desired time-delayed IJ rhythm pattern is sent from the line 10 to the sound source 0'.
At the same time, it is outputted through line 8 and input into an OR circuit 17 together with the rhythm pattern from line 2, where it is synthesized and outputted to sound source 1 through line 9. FIG. 3 shows a specific example of the low frequency clock generator 20 of FIG. That is, oscillator 2
The square wave generated at line 1 is divided by frequency divider 22 and output to line 18.
, 19. Line 18 is led to gate 14 and line 19 is led to select gate 15 to control each. FIG. 4 shows a specific example of the gate 14 shown in FIG.

That is, the switch output is input to an AND gate 31 together with the output of line 18 of the low frequency clock generator 20 via an inverter, and the output thereof is input to an AND gate 32 together with the branched output from line la to be output on line 3. It is. AND gate 3 when the switch is off
Since the output of 1 is "0", the gate 32 is closed and no output is made to line 3. When SW is on, the gate is opened for a certain period of time by the divided output 18 of the low frequency clock generator 20, and the rhythm pattern is output from the ROM 13 to the line 3 and input to the select gate 15. FIG. 5 shows a specific example of the select gate 15 shown in FIG.

That is, the output of the divided output line 19 of the low frequency clock generator 20 is decoded by a multiplexer (line decoder) 41, which opens one of the AND gates 42 and passes it through one of its output lines S, ~Sn to the ROM.
The rhythm pattern is guided to the shift register 16. This rhythm pattern is stored in the shift register 16 by a read pulse from line 4. Next, at the rising edge of the shift clock from line 7, the signal is shifted by the desired number of pulses and output with a certain time delay. In this case, the output of the low frequency clock generator 20 is not synchronized with the measures, so
The select gate 15 opens as if at random, and a different rhythm can be obtained for each measure. This state of random rhythm is not musically disjointed; for example, only the cymbals on the ROM output line play different rhythms for each bar, and the other percussion instruments on the ROM output line keep a constant rhythm. The output of line 8, which is a branch of the output of the shift register, is added to the main pulse of line 2 and guided to source 1.

Furthermore, if the signal is input through line 10 to another sound source 0, further variations can be obtained. As explained above, according to the present invention, the rhythm pattern output from the storage device is branched into two lines without increasing the capacity of the rhythm pattern stored in the ROM, and the rhythm pattern of one of the lines is divided into two lines. The IJ rhythm pattern with the desired time delay is created by a variation circuit in which the select gate that selects the address of the shift register to be inputted is controlled by the low frequency clock of the low frequency clock generator, and this is branched into the rhythm pattern of the other line. By synthesizing the rhythm patterns, you can easily and musically create variations in rhythm patterns.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a conventional example, FIG. 2 is an explanatory diagram showing the configuration of an embodiment of the present invention, and FIGS. 3 to 5 are specific circuit examples of main parts of the embodiment of FIG. In the figure, 11 is a rhythm clock generator, 12 is an address counter, and 13 is a storage device (RO
M), 14 is a gate, 15 is a select gate, 16 is a shift register, 17 is an OR circuit, two low frequency clock generators, and 21 is a delay circuit. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Scope of Claims] 1. An address counter that generates an address signal for reading a memory device according to a rhythm clock, a memory device that outputs a pre-stored rhythm pattern using the address signal, and means for branching the output rhythm pattern into two lines. , a variation circuit that creates a desired time-delayed rhythm pattern from the rhythm pattern of one branched line, and means for synthesizing the rhythm pattern of the other branched line and the time-delayed rhythm pattern of the variation circuit. , and a circuit for generating a low frequency clock for controlling the means for branching into the two lines and the variation circuit for creating the time-delayed rhythm pattern. 2. The variation circuit has a select gate that selects an address of a shift register to which the rhythm pattern of one of the branched lines is input by the low frequency clock of the low frequency clock generator, and a rhythm pattern that is input to the select gate. 2. The rhythm pattern variation device according to claim 1, further comprising a shift register which is shifted by said rhythm clock and delayed by a desired time. 3. The rhythm pattern variation device according to claim 1, wherein the circuit for generating the low frequency clock generates a plurality of low frequency clocks having different frequencies.