JPS6025832B2 - Chip selection circuit in semiconductor devices - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to MOSFETs used when selecting a semiconductor device for operation or when selecting it to distinguish it from other semiconductor devices.
The present invention relates to a chip selection circuit consisting of:

In recent years, complex electronic devices have been constructed using semiconductor integrated circuits, and as a result, the amount of information stored in integrated circuit devices has increased, and large-capacity memory devices have come to be required.

Although it is possible to construct a large-capacity memory by incorporating it into a single semiconductor substrate, it is also possible to construct a large-capacity memory by dividing it into relatively small-capacity parts and using a plurality of relatively small-capacity memories that can be easily manufactured. be able to. Not only when multiple memory devices are used as described above, but also when multiple semiconductor devices are combined to control the operation of electronic equipment, the content of information from multiple installed semiconductor chips is A semiconductor device to be operated in accordance with the input information is appropriately selected, an operation corresponding to the input information is executed, and an output signal is generated. The present invention provides a selection circuit for selecting a semiconductor device to be operated from among the plurality of chips in a circuit using a plurality of semiconductor chips as described above. The present invention will now be described in detail with reference to Examples. FIG. 1 is a basic configuration diagram according to the present invention. The feature of the present invention is the part shown at 1 in FIG. That is, the sources and drains of the two MOSFETs Tr and Tr2 are connected in series at node 2, forming an output line A. T
The drain 3 of the transistor r, is connected to the power supply Vcc, and the source of the transistor Tr2 is grounded. Moreover, the above MOSFETTr,,T
r2 is designed to be in the OFF state when the gate electrodes 5 and 6 are connected to the respective sources 2 and 4 and the respective MOSFETs are formed of the enhancement type. However, by forming one of MOSFETs Tr and Tr2 as a depletion type MOSFET and the other as an enhancement type MOSFET,
Node 2 can be at Vcc or OV. Assuming that Tr is a depletion type M○SFET and Tr2
is an enhancement type MOSFET, then T
2 is off, node 2 becomes the same potential as Vcc through Tr, and Vcc is applied to output line A. Conversely, if Tr is an enhancement type MOSFET, T
When r2 is a depletion type MOSFET, Tr is off, node 2 is grounded through Tr2, and the output line is at ground level. As above, Tr,,T
The level of the signal delivered to output line A is determined by selecting the type of r2. By forming either Tr or Tr2 with an enhancement type MOSFET, the DC path from the power supply Vcc to the ground line is cut off, so there is no current consumption other than leakage current. The polarity Tr,, Tr2 of the power supply Vcc is positive when it is an N-channel MOSFET, and it is positive when it is a P-channel MOSFET.
is negative if . As mentioned above, by determining the types of MOSFETs Tr and Tr2 in advance according to the program, the level of the signal led out to the output line A is determined, but the semiconductor chip operated by such a signal level setting circuit A signal is formed for selecting.

That is, the pre-programmed level A output from the node 2 of the pair of MOSFETs shown in FIG. According to the truth table input to the circuit 8 and shown in the following table, the selection or non-selection of the semiconductor chip to which the output Q is given is determined depending on whether the exclusive OR circuit output 9 is "0" or "1". In other words, it is determined whether the chip selection signal is an active signal that selects at a high level or an active low signal that selects at a low level. M.O.S.
The selection is made by using an FET.

Note that for logic "0" and "1", positive logic or negative logic may be used depending on whether Tr and Tr2 are N-channel MOSFETs or P-channel MOSFETs. According to the selection circuit shown in FIG. 1, the selection method can be easily extended to a large number of semiconductor devices.

In other words, by increasing the number of chip selection signals 7, the number of semiconductor devices that can be selected increases by a factor of two, and a chip selection signal line dedicated to each semiconductor device is no longer required, and a common chip selection signal line can be used. Figure 2 shows an expanded application example. In this embodiment, four semiconductor devices 11, 12, 1
3 and 14 are provided, and the chip to be operated is selected based on the signals applied to the two chip selection signal lines 15 and 16 and the contents programmed in advance in the selection circuit of each semiconductor device. That is, the semiconductor device 1 in FIG. 2 is T.
r,. , Tr, 3 are depletion type MOSFEs.
T is the chip selection signal line CS. /cs. ,S,/cs
, are both selected at a low level, and the semiconductor devices 1 and 2 are Tr
, 5, Tr, 8 are depletion type MOSFETs.
So CS. /cs. is selected at a high level and CS, /cs, is selected at a low level, and in the semiconductor device 13, Tr2o and Tr2 are depletion type MOSFETs, and C80/cs is selected at a high level.
. is selected at a low level, CS,/cs, is selected at a high level,
In the semiconductor device 14, Tr24 and Tr26 are depletion type MOSFETs, C3o/cso, CS, /cs.
, are both selected at a high level. In Figure 2, T
r, ] ~ When Tr26 is an N-channel MOSFET and uses positive logic, the node Q, of the selection circuit of each semiconductor device is
．． ~Q, 4, a semiconductor device that outputs a high level is selected. In the above embodiment, the program circuit for chip selection is configured using a pair of MOSFETs connected in series, and the circuit has no current consumption. However, if a small amount of current consumption is allowed, As shown in Figure 3a, MOSFET
Either leave ETTr2 and replace MOSFETTr with a pull-up resistor, or replace MOSFETTr as shown in b.
It is also possible to replace MOSFET Tr2 with a pull-down resistor while leaving r.

As the pull-up resistor and pull-down resistor, a polycrystalline silicon resistor or a diffused resistor, an enhancement type MOSFET with high on-resistance, a depletion type MOSFET with high on-resistance, etc. can be used. As described above, according to the present invention, when selecting semiconductor devices of the same type, especially in the case of a semiconductor memory, the chip selection signal can be handled in the same manner as an address signal, which is effective for memory expansion. Furthermore, the present invention provides a method for determining whether the MOSFET in the selection circuit is a depletion type or an enhancement type.
Since this is a selection method that programs "1" and "0" of the chip selection signal, in the case of a mask ROM that determines "1" and "0" depending on the enhancement type and depletion type of the memory MOSFET, the memory MOSFET and By using MOSFETs of the same channel as selection circuits, by using the same mask, RO
M data and chip selection data can be written. Especially when a large amount of information is shared between several ROMs,
The present invention can use a mask ROM that distinguishes fixed data according to enhancement type and depletion type, and by changing one mask, R
It is possible to change the OM and the program for chip selection, and is most effective in processing a large number of ROMs.

[Brief explanation of the drawing]

FIG. 1 is a basic circuit diagram showing an embodiment of the invention, FIG. 2 is a circuit diagram showing an applied example of the invention, and FIGS. 3a and 3b are circuit diagrams showing other embodiments. Tr,, Tr2: MOSFET, 2: Node, 5, 6...
- Gate electrodes, 11, 12, 13, 14: semiconductor device.
Figure 'Figure 3 ~ Job

Claims (1)

[Claims] 1. In a circuit that selects one memory chip from a plurality of semiconductor memory circuits, an enhancement type MOSFET and a depletion type MOSFET are connected in series between the power supplies, and a signal from the connection point of both of the above MOSFETs is inputted to one side, and the chip is inputted to the other side. A chip selection circuit for a semiconductor device, comprising: an exclusive OR circuit which receives an address signal and outputs a chip selection signal; and wherein selection of a semiconductor memory chip is programmed by the depletion type MOSFET. .