JPS6025835B2 - semiconductor memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory circuit using a plurality of memory cells each composed of one transistor and one capacitor.

A conventional circuit is shown in FIG.

In the figure, 1 is the storage capacity for storing "1" or "0" data, and 2 is the switching for reading or writing data in storage capacity 1, or for holding the data stored in storage capacity 1. transistor, 1
0 is a memory cell consisting of storage capacity 1 transistor 2, 3
4 is a parasitic capacitance attached to a bit line that transmits data to the memory cell 10', and 4 is an external power supply necessary to form a storage capacitor. Generally, 4 is the highest level power supply used in semiconductor memory circuits. In the circuit shown in Figure 1, the voltage amplitude read on the bit line when a voltage is applied to the word line is determined by the voltage and capacitance of storage capacitor 1 and bit line capacitor 3, and this relationship is expressed by the following equation. It is generally known that (for example,
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LSC-8 NO. 50Ct. 197 is. 81 Dew). ΔVB=Kichiji Tuition Fee Here, Cs is the storage capacity of the memory cell, CB is the capacitance of the bit line, and ΔVB is the voltage fluctuation of the bit line when reading the cell.

Vso and VBo are the voltages at each node of the capacitances Cs and CB before reading, respectively. According to the above formula, in order to increase the read voltage amplitude ΔVB, the storage voltage Vs.

There are two methods: increasing the bit line capacitance CB or decreasing the ratio of the bit line capacitance CB to the storage capacitance Cs. Among these, various methods have been considered for the latter method, but the former method has not been sufficient as described below. In a semiconductor memory circuit using a memory cell with one transistor and one capacity, a channel capacitor is used as the memory capacitor because a high degree of integration can be obtained. Therefore, one electrode of the memory capacitor is connected to the semiconductor to form a channel. It is generally connected to the highest power supply used in the memory circuit.

Second, a schematic diagram of a cross-sectional structure of a memory cell consisting of one transistor and one capacitor is shown. In Figure 2, 50
is a P-type semiconductor substrate, 51 and 52 are N-type semiconductor regions, and 53 is a P-type semiconductor substrate.
, 54 are oxide films, and 55 and 56 are electrodes, which include a channel portion 52a that is combined with the N-type semiconductor region 52, and an oxide film 54a.
and an electrode 55 constitute a storage capacitor 1, and a P-type semiconductor 50, N-type semiconductor regions 51 and 52, an oxide film 53, and an electrode 56 constitute a transistor 2.

The word line is connected to electrode 56 and the bit line is connected to N type semiconductor region 51. As is clear from FIG. 2, the structure of the storage capacitor section is very similar to that of a MOS transistor, and can be said to be a MOS transistor without a drain. In other words, it can be easily inferred that the characteristics of the storage capacity will be the same as those of the MOS transistor. Now, if we associate the region 52a where the channel is formed with the source of the transistor 2 and the electrode 55 to which power is applied with the gate of the transistor 2, the gate electrode 55
When the voltage VDo is applied to , the highest level of the voltage Vso of the region where a channel is formed, that is, the source, is given by the following equation. Vs.

=V. D-VT Here, VT is the voltage required to form a channel, and is determined by the thickness of the insulating film, dielectric constant, etc.

In other words, the storage voltage is equal to the gate voltage (power supply voltage) minus the threshold voltage.

The present invention has been made in order to improve the above-mentioned drawbacks of conventional semiconductor memory circuits, and the voltage applied to the gate of the memory capacitor is made higher than the power supply voltage used in this semiconductor memory circuit. The purpose is to increase the

FIG. 3 is a circuit diagram showing one embodiment of the present invention. Third
In the figure, the circuit operation of the present invention is basically the same as that of the conventional circuit, but the gate electrode of the storage capacitor is at V. . is set to a higher voltage. FIG. 3 shows an embodiment in which a voltage higher than Voo is applied using an oscillation circuit and a booster circuit. FIG. 4 shows an example of a circuit that is a more specific version of the circuit shown in FIG. In FIG. 4, 5 is a boosting capacitor CP that supplies charge for boosting, 6 is a rectifying transistor to give directionality to the charge supply, and 7 is a voltage for increasing the final level of boosting. 8 is a parasitic capacitance Ct, and 9 is a capacitor CN which equivalently represents the sum of the storage capacitance and the parasitic capacitance of each memory cell. In the semiconductor memory circuit shown in FIG. 4, if the Voo power supply is now turned on from a momentary cut-off state, nodes A and B are charged by transistor 7 to Voo-VT and VoD-2VT, respectively.
At the same time, the output 0 of the oscillation circuit also begins to oscillate and the voltage starts to rise, but for ease of understanding, the explanation will be made assuming that ◇ oscillates after each of the above nodes reaches a predetermined level. Now, when J rises after the above-mentioned nodes A and B reach Voo-VT and Voo-2VT, respectively, charge is supplied to node B through transistor 6, and its level increases by the following equation.

Next, when the signal ◇ falls, the voltage at node A decreases due to the coupling with the boost capacitor 7, but the voltage at node B increases between the gate and source of transistor 6. Since the transistor 6 is short-circuited, the transistor 6 becomes non-conductive and does not drop.

Therefore, the voltage at node B gradually increases as a result of the repetition of '. Then, when the voltage at node A reaches the highest level in terms of the circuit, the level at node B stops rising. The highest level of node A at this time is as shown in the following equation. V Misakimatsu = V Blood - VT + C; Verse V Plate Also, the level of node B at this time is higher than that of node A, and has a value lowered by the voltage.

Therefore, V skin = V blood - VT + C; reed; V blood, but in the above formula, it can be easily realized that CP>>Ct, so V'.

. =2(V..-V,)〉V. . However, 2V, <Vo.

shall be. Therefore, it becomes possible to increase the storage voltage.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional semiconductor memory circuit, FIG. 2 is a cross-sectional view showing the structure of a memory cell, FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. 4 is a modification of FIG. 3. A circuit diagram showing a specific embodiment, FIG. 5 is a waveform diagram for explaining the circuit operation of FIG. 4. In the figure, 1 is a capacitor, 2 is an insulated gate field effect transistor, and 10 is a memory cell. Note that the same reference numerals in the figures indicate the same or corresponding parts. Figure 1 *2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1. An insulated gate field effect transistor having one main electrode connected to a bit line and a gate electrode connected to a word line, and one electrode connected to the other main electrode of the insulated gate field effect transistor, In a memory cell comprising a capacitor whose other electrode is connected to a DC voltage, the memory cell is provided with boosting means for making the voltage applied to the other electrode of the capacitor higher than the power supply voltage. Characteristic semiconductor memory circuit. 2. The semiconductor memory circuit according to claim 1, wherein the boosting means includes an oscillation circuit, a capacitor, and a switching element, and receives an output of the oscillation circuit and boosts the voltage.