JPS6025906B2 - logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to logic circuits, and more particularly to logic circuits with reduced storage time and increased switching speed.

In saturation type logic circuits, it has been conventionally attempted to reduce the storage time of transistors by performing gold (Au) diffusion. Furthermore, when gold diffusion is not performed, a Schottky barrier diode clamp is used to reduce the storage time. The present invention uses npn transistors and pnp transistors without using Schottky barrier diodes to reduce storage time and increase the switching speed of logic circuits, and is particularly easy to implement in integrated circuits. It is. SUMMARY OF THE INVENTION An object of the present invention is to provide a high switching speed logic circuit that is easy to implement in an integrated circuit.

To achieve this objective, the logic circuit according to the present invention is an np
a pnp transistor having an emitter connected to the base of the npn transistor and a base of the npn transistor, and a pnp transistor having a base connected to the collector of the npn transistor to allow a part of the base current of the npn transistor to flow;
The transistor and the pnp transistor are formed in the same land of an n-type semiconductor layer formed on a p-type substrate, and the n-type semiconductor layer in the land has a transistor that becomes the base of the npn transistor and the emitter of the pnp transistor. The first p-type region and the first p-type region are provided separated by the n-type semiconductor layer, and the second p-type region which becomes the collector of the np transistor and the first p-type region are separated from each other by the n-type semiconductor layer. an n-type region formed within a type region and serving as an emitter of the npn transistor; and an n-type buried layer formed between a nuclear p-type substrate and an n-type semiconductor layer, and the n-type buried layer is It is characterized in that it is provided at least in a region directly below the emitter electrode of the npn transistor, and is not provided in at least a region directly below the base electrode of the npn transistor. Embodiments of the logic circuit according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a basic circuit of a logic circuit according to the present invention.

In Figure 1, the base of the npn transistor Q, is pn
It is connected to the input terminal together with the emitter of the p-transistor Q2, the collector output of the transistor Q is connected to the base of the transistor Q2, and the emitter of the transistor Q and the collector of the transistor Q2 are connected in common. 1st
In the circuit connected as shown in the figure, the input current 18 first flows through the transistor Q. When the transistor Q is turned on, the collector voltage of the transistor Q drops and the transistor Q2 enters the active region, causing a current to flow through the transistor Q2. transistor Q
Between the emitter and collector of 2 is the base of transistor Q.
Since it is clamped to the emitter voltage VBE, it is always unsaturated, and the base current 181 of the transistor Q in a steady state becomes 18, = IB - (8pnp + 1) IB2, and the saturation control of the transistor Q is performed. .

Therefore, at turn-on, the input current itself drives the transistor Q, so the turn-on time remains unchanged, and at turn-off, saturation control is performed, so the turn-off time is short or fast. FIG. 2 shows an example of a logic circuit constructed using the basic circuit of FIG. 1 according to the present invention, and the figure shows an emitter input transistor Q.
In this figure, transistor Q2 is always in the active region, and (81) times the base current of transistor Q2 is shunted to reduce the reverse current of transistor Q.

Although the transistors Q and Q2 of FIGS. 1 and 2 can also be constituted by discrete transistors, this circuit can be formed as the same isolation transistor of an integrated circuit, which is one of the circuits according to the invention. It is a characteristic. Figures 3A and B show that
FIG. 3A shows an equivalent circuit of the basic circuit of FIG. 1, and FIG. 3B shows a cross-sectional view of this circuit when it is configured as an integrated circuit. In FIG. 3B, 1 is a p-type silicon substrate, 2 is an n-type buried layer, 3 is an n-type layer, 4 and 5 are p-type layers, 7 is an n-type layer, 8 is a p-type layer, and 9 is an n+ type layer, n in the figure
The emitter-base and collector of the npn transistor are formed by the type layer 9, the p-type layer 8 and the n-type layer 7, and the emitter-base and collector of the pnp transistor are formed by the p-type layer 6, the n-type layer 8 and the p-type layer 4. A collector is formed.

That is, the base of the npn transistor and the emitter of the pnp transistor are formed by the p-type layer 8, and the input terminal 8
a, the collector of the npn transistor and the pnp
The base of the transistor is formed by the n-type layer 7 and connected to the output terminal 7a, and the emitter of the npn transistor is formed by the n-type diffusion layer 9. Further, the collector of the pnp transistor, that is, the p-type layer 4 is grounded. In manufacturing an integrated circuit as shown in FIG. 3B, pnp
Transistor Q2 is connected to the isolation region and n
By narrowing the effective base width of the pnp transistor by performing diffusion in the same process as when manufacturing the base of the pn transistor, and further selecting the concentration and thickness of the base region 6 appropriately, the current increase rate of the pnp transistor can be easily increased to 8. can be set to 10 or more. As explained in detail above, the present invention aims to reduce the storage time by performing saturation control at turn-off without performing gold diffusion or using a Schottky barrier diode, and is particularly applicable to integrated circuits. Since it can be manufactured in a very simple process, it is extremely effective in manufacturing integrated circuits.

[Brief explanation of the drawing]

Fig. 1 is a basic circuit showing the principle of a logic circuit according to the present invention, Fig. 2 is an embodiment of a logic circuit according to the present invention, and Fig. 3 A and B are circuits according to the present invention formed using an integrated circuit. A cross-sectional view of one example of the case is shown. In the figure, Q. is an npn transistor, and Q2 is a pnp transistor. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1 has an npn transistor, an emitter is connected to the base of the npn transistor, a pnp transistor has a base connected to the collector of the npn transistor, and allows a part of the base current of the npn transistor to flow; The pnp transistor is formed in the same land of an n-type semiconductor layer formed on a p-type substrate, and the n-type semiconductor layer in the land has a first transistor that becomes the base of the npn transistor and the emitter of the pnp transistor. A p-type region and the first p-type region are provided to be separated from each other via the n-type semiconductor layer, and a second p-type region serving as the collector of the pnp transistor and a region within the first p-type region and an n-type buried layer formed between the p-type substrate and the n-type semiconductor layer, the n-type buried layer being formed at least in the npn transistor.
Provided in the area directly under the emitter electrode of the n-transistor,
A logic circuit characterized in that it is not provided at least in a region immediately below a base electrode of the npn transistor.