JPS6026341B2 - Control signal detection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control signal detection method for a facsimile apparatus to receive a control signal from the other party's facsimile apparatus in its own transmission signal.

In a FAX device such as a facsimile (hereinafter referred to as FMX) transmitter, control signals such as stop of reception and emergency call may be transmitted from the AX device in response to transmission signals such as image signals. After receiving the signal, it is required to perform control operations such as interrupting transmission and displaying a call depending on the content of the control signal.

However, in general, FAX machines are connected by a single two-wire telephone line, and the transmission signals from the own device and the control signals from the other device are generated simultaneously on the same line. It is necessary to distinguish and detect the control signal from the other party, and even if the transmitting circuit and receiving circuit are separated at the line terminal using a three-turn transformer, etc., the level difference between them and the control signal from the three-turn transformer, etc. Due to the reduction in echo attenuation, the transmitted signal goes around to the receiving circuit,
It has become necessary to distinguish between a transmitted signal and a control signal and then detect the control signal, and various means have been proposed in the past. In other words, the simplest method is one in which the control signal is detected only during the own phase signal transmission period, since the phase signal that regulates the synchronized operation between the transmitting side and the receiving side is inserted between the image signals. However, since the control signal cannot be detected unless it is during the phase signal transmission period, there is a drawback that there is a delay in receiving the control signal.

In addition, the same component as the transmitter signal is detected from the own transmitter signal using a band radio wave detector and a signal detector, and the control signal can be detected only when this detection power is not generated. However, as the circuit configuration becomes more complex, delayed operation occurs based on the transient response characteristics of the band wave reactor, resulting in drawbacks such as the risk of malfunction.

Note that other methods also have drawbacks such as a complicated circuit configuration and unstable operation, and at present none of them is truly suitable.

The purpose of the present invention is to eliminate all the drawbacks of the conventional art, and detects changes in the transmitted signal to generate a pulse signal, and uses this pulse signal to start a time regulating means to generate pulses within a predetermined time. By making it possible to detect a control signal using a time-up output that is generated only when the signal does not occur again, a control signal detection method that has a simple configuration and reliable operation is provided.

Hereinafter, details of the present invention will be explained with reference to figures showing examples.

FIG. 1 is a block diagram showing the configuration. A document is scanned by a photoelectric conversion element, etc., and an image signal Sv corresponding to the brightness of each pixel arranged on a scanning line is applied to a processing circuit VPR. In addition to processing such as signal insertion, a modulation circuit MOD modulates a carrier wave such as an audio frequency signal that can be transmitted over a transmission path such as a telephone line,
The modulated carrier wave is transmitted to the transmission line L as a transmission signal St via a hybrid circuit HYB such as a three-turn transformer.

On the other hand, a control signal S from the other party arrives via the transmission path L.
c is given to the belt wave reactor BPF which has a passage characteristic according to the frequency of the control signal via the hybrid circuit HYB. The waveform shaping circuit WF converts the signal into a pulse waveform that repeats high level (hereinafter referred to as "H") and low level (hereinafter referred to as "L").

In addition, the output of the processing circuit VPR is also given to a set pulse generation circuit RPG such as a differentiating circuit, and as shown in the time chart of FIG. 2, which shows the waveforms of each part in FIG. That is, the IJ set pulse b is generated as a pulse signal by detecting a change in the transmission signal.

This reset pulse b passes through an OR gate G, and resets a flip-flop circuit (hereinafter referred to as FFC) FF, and also passes through an OR gate G2 and becomes its output e, which is the input 1 of an exclusive OR (hereinafter referred to as EXOR) gate G3. given to.

Then, at this time, input 2 of EXOR gate G3 is FFC
・FF2 is “L” because it is in the reset state, and EXOR
The output g of the gate G3 is “H” only during the period of the reset pulse b.
”, the counter CT as a time adjustment means is reset and activated at the same time, and starts counting the clock pulse PC given from a separately provided clock pulse generator.The counter CT , First, count output Q after L from the start of counting.
, then a count output Q2 is generated, and a count output Q3 is generated after a lapse of time, and in each case each count output Q, ~Q3 is set to "H", but at first F
Since FC/FF2 is in the reset state and AND gate G5 is off, the count output Q,, Q2 becomes invalid, and the FFC/FF is set by the "H" of the count output Q as a time-up output, and its output Q is set to "H" as shown in Figure 2 d, and this is applied to the input 1 of EXOR gate G3 via OR gate ○2, so the output g of gate ○3 becomes "H" again, which causes the counter to CT is reset.

In addition, the output Q of FFC/FF is “L” as it is set.
When the reset state of FFC/FF2 is released and the received pulse c converted into a pulse waveform from the waveform shaping circuit WF becomes "H", this causes the FF
C.FF2 is set, and its output Q becomes "H" as shown in Figure 2 f, which changes the output g of EXOR gate G3 to "L", releases the reset state of the counter CT, and starts counting again. Let it start.

Then, the count CT becomes the count output Q, as described above.
, Q2 are set to "H" sequentially, but the time t from the start of counting until the count output Q, is generated is determined by the control signal Sc.
is slightly smaller than the period T of the received pulse c determined by the frequency of , whereas the time t2 until the count output Q2 is generated is set slightly larger than the period T.
The count output Q, is applied to the input 1 of the AND gate G4, and the count output Q2 is applied to the AN via the inverter IV.
When applied to input 2 of D gate G4, the time difference between the two is −t
, is obtained as the gate pulse h from the output of the AND gate G4.

This gate pulse is applied to the set input J of FFC/FF3 via AND gate G5, which is ON only when FFC/FF2 is set, and during this period, the received pulse c becomes "H". When it is applied to the clock pulse input CP of FFC/FF8, the FFC/FF
3 is in the set state, and the output Q is as shown in Figure 2 j''
This state is maintained as "H".

Note that if the reset pulse b is generated again during the predetermined time t3 after the counter CT is activated by the reset pulse b and starts counting operation until the count output Q is generated, the count CT is reset and the counting operation is restarted from the beginning. Since it starts from , as long as this state continues, FFC/FF
2 is not set, and FFC/FF3 is set by the received pulse c.
is never set.

That is, by setting FFC・FF3, the control signal Sc
is detected, and this detection becomes possible after a predetermined time t3 has elapsed after the change in the transmission number a, and if the transmission number a changes during the elapse of the predetermined time t3, the detection is blocked. Ru.

Therefore, as shown in Fig. 2c, due to the change in the transmitter number a, unnecessary signals N, ~N
No detection is performed during the period in which 4 occurs, and unnecessary signals N, ~
N4 disappears, there is no change in the transmission number a, and the received pulse c
Since the reception pulse c is detected only under conditions where it does not affect the control signal Sc, it is possible to stably receive the control signal Sc.

The output output Q of the FFC/FF3 is given to the receiving circuit RC as a control signal detection command, and thereby the receiving circuit RC generates a control output OUT according to the control signal Sc, and its own FA
A predetermined control operation is performed in the X device.

Note that FFC/FF3 is reset by the IJ set signal from the receiving circuit RC, but as shown in the time chart in Figure 3, which is a further extension of the time chart in Figure 2 and the time axis is scaled down, the image of transmission number a is Receive the phase signal Sp during the planking period B provided between the signals P and P.
C receives the signal and generates a reset signal.

Therefore, as shown in Figure 3i, the output Q of FFC/FF3 is
is generated as "H'', and the receiving circuit RC confirms that this has occurred N times in succession and then produces the control output OUT, so that the control signal Sc is reliably received.

In addition, if the count output Q2 is generated from the counter CT when the FFC/FF is in the set state, this causes the FFC
FC・FF is reset, and accordingly FFC
・Since FF2 is also reset, IJ of FFC・FF,
During a period corresponding to the time difference between the set and the reset of FFC/FF2, the output g of the EXOR gate G3 becomes "H" and the counter CT is reset, and the count output Q. ,Q
By repeating the occurrence of 2, FF
A D-type FFC is used for C/FF3, and the output i of the AND gate G5 is applied to the data input of the D-type FFC, regardless of the IJ set signal from the receiving circuit RC, and the set/reset is performed by the control signal c as a clock pulse. It may be something you do.

In addition, in order to confirm the period T of the received pulse c according to the frequency of the control signal Sc, count outputs Q, , Q2 and F
Although FC, FF, etc. are used, these can be omitted, and the configuration of the embodiment can be modified in various ways.

Note that documents handled by a FAX machine generally have a lot of white margins, and this part does not change in the image signal, so the conditions for detecting the control signal Sc are established on an extremely large number of occasions during the transmission of a series of image signals. The control signal Sc can be promptly received.

As is clear from the above description, according to the present invention, the reliable detection of the control signal is quickly performed not only during the blank period but also during the transmission of the image signal by a simple horizontal operation. A unique effect can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a time chart showing waveforms of various parts in Fig. 1, and Fig. 3 is a time chart that is an extension of Fig. 2 and the time axis is scaled down. . PRO...Reset pulse generation circuit, CT...
...Counter, FF,, FF2, FF3...FFC
(flip-flop circuit), G,, G2...OR gate, G3...EXOR (exclusive OR) gate, G4, G
5...AND gate, IV...Inverter. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. In a facsimile device that receives a control signal from the other party's facsimile device during transmission of a transmission number and performs a control operation according to the control signal, means for detecting a change in the transmission number and generates a pulse signal; . A control signal detection method, comprising: time regulating means that is activated by the pulse signal and generates a time-up output when the pulse signal does not occur again within a predetermined period of time to enable detection of the control signal.