JPS6027049B2 - Logical motion tracking device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logical operation tracking device that stores and holds information (information to be diagnosed) related to the logical operation of a logical device, particularly an information processing device.

A logical operation tracking device that is subordinate to an information processing device sequentially writes diagnostic information obtained from the information processing device to a storage device at fixed time intervals, and stores the information when a fault occurs in the information processing device and a fault detection signal is output. By stopping writing to the device, hardware history information for a certain period of time up to the occurrence of a failure is recorded.

However, in such a configuration, when the information processing device is hung up or in a loop state, writing continues even though the information processing device is not operating, so there is no effective storage capacity at the time the failure detection signal is output. There are inconveniences such as the diagnostic information disappearing and the need to increase the storage capacity of the storage device in order to avoid such inconveniences. SUMMARY OF THE INVENTION An object of the present invention is to provide a logical operation tracking device that eliminates the above-mentioned disadvantages. The present invention is characterized by a means for detecting a pause signal issued when an information processing device (generally a logic device) is in a dormant state and inhibiting writing to the storage device after a certain period of time; Moreover, the present invention includes means for restarting the write operation of the storage device when no failure is detected.

In this case, the dormant state of an information processing device refers to a waiting state in which it is required to proceed from one process to the next.Specifically, after issuing a memory access request, the data is read out. , a conversion period from a logical address to a real address, a state in which an instruction cannot be executed for some reason (not detected as a failure), etc. Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a logical operation tracking device that is an embodiment of the present invention.

a data register 2 that holds diagnostic information 1 provided from an information processing device serving as a logical device to be diagnosed; a storage device 3;
The device of this embodiment is comprised of an address counter 5 and an address decoder 4 for selecting the last write address, and a write control circuit 6. The write control circuit 6 receives a pause signal and a failure detection signal from the information processing device,
A write pulse, which is the write timing for the storage device 3, is given. FIG. 2 is a detailed diagram of the write control circuit 6.

The write control circuit 6 receives a pause signal from the information processing device “
A counter 6a that increments 11 at fixed time intervals only when the value is 1”
Then, a decoder 6b that decodes the contents of this counter 6a and outputs a "1" output only when the value of the counter reaches a certain value, for example, "16", and a latch 6c that holds the output of this decoder. The write control circuit 6 also has a latch 6d that latches the failure detection signal and an AND gate 6f that ANDs the output of this latch and the write pulse, which are similar to the conventional device.The latch 6d is It is reset by a reset signal issued when the device power is turned on, etc.The outputs of latches 6c and 6d are ORed by an OR gate 6e, and the write pulse and AND are cut off by an AND gate 6f.The output of the AND gate 6f is output from the memory device. 3
Address counter 5 is also used as a write permission signal for
It is sent out as the 11th signal. Furthermore, inverter 6
g is provided for the purpose of resetting the counter 6d when the pause signal is "0". Next, the operation will be explained.

When neither a fault detection signal nor a halt signal is issued from the information processing device (logical device to be diagnosed) (when both signals are “0”)
Both latches 6c and 6d are reset, and a constant period write pulse is sent out as a write enable signal and a 11 signal via an AND gate 6f.

Therefore, the information to be diagnosed is written into the storage device 3 while sequentially changing the addresses to 11. When a failure occurs in the information processing device and a failure detection signal is output, the latch 6d is immediately set and the AND gate 6f is inhibited.

Therefore, the sending of the write permission signal and the 11 signal is suppressed, and the write operation of the storage device 3 is stopped. The operations up to this point are the same as those of the conventional device and are not new.

The present invention is characterized by the following operation. That is, if a pause signal is issued from the information processing device while writing the information to be diagnosed (no fault detection signal is issued), the counter 6a
counts up at regular intervals, and the count value reaches “16”.
When the output of the decoder 6b reaches "1", the latch 6c is set.

That is, the latch 6c is set after a certain period of time determined by the logic of the counter 6a and decoder 6b after the generation of the pause signal. This time can be arbitrarily set by the count value at which the output of the decoder 6b becomes "1". By setting the latch 6c, the AND gate 6f is inhibited, the write permission signal and the 11 signal are no longer sent, and the write operation of the storage device 3 is stopped. This state is 0 when the pause signal disappears.
Continue until ). When the pause signal disappears, the counter 6a is reset by the output of the inverter 6g,
At the same time, the latch 6c is reset, the AND gate 6f is released from the inhibition, and the write operation of the memory device 3 is restarted.
In this way, when the information processing device enters the hibernation state, writing to the storage device 3 is stopped after a certain period of time.

In conventional devices, such information is written, and the storage capacity of the storage device needs to be sufficiently large. As described above, the logical operation tracking device of the present invention separates the failure state from the hibernation state and prevents writing of unnecessary information during the hibernation state.As a result, the storage device for storing information to be diagnosed does not have to have a large capacity. It is also possible to obtain diagnostic information useful for failure analysis of information processing equipment, etc.

Furthermore, reducing the storage capacity of a storage device means that the total amount of information stored in the storage device will be reduced, resulting in less wasteful information, which has the benefit of improving the efficiency of failure analysis based on stored information. There is also.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a logic operation tracking device according to the present invention, and FIG. 2 is a detailed block diagram of the write control circuit in FIG. 1. 2...Data register, 3...Storage device, 4...
Address decoder, 5...Address counter, 6...
・Write control circuit, 6a...counter, 6b...decoder,
6c, 6d...Latch, 6e...OR gate, 6f...AND gate. Figure 1 Figure 2

Claims (1)

[Claims] 1. In a logical operation tracking device that sequentially writes information regarding the logical operation of a logical device into a storage means and stops the writing operation when a failure is detected, there is no waiting time for the logical device to proceed from one logical operation to the next logical operation. means for inhibiting a write operation of the storage means after a predetermined time upon detecting a pause signal issued from the logic device when the logic device is in the state; A logical operation tracking device comprising: means for restarting a write operation.