JPS6027434B2 - Aggregation method in electronic cash register - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an aggregation method in an electronic cash register that has an internal clock function and automatically aggregates sales within a designated time period.

Conventional electronic cash registers usually perform settlement at the end of the day, so data can be collected on a daily basis, but data cannot be collected on an arbitrary time basis.

For this reason, although it is possible to know what kind of products sold and how much they sold on a daily basis, it is not possible to know the sales status at each time period of the day. For example, if you can know the sales status every two hours, you can create more detailed data and use it for management and management. The present invention has been made in view of the above points, and by setting the start time for starting aggregation by time zone and the division time of the time zone, the aggregation within each set time zone is automatically performed. The purpose of this invention is to provide an aggregation method in an electronic cash register that can perform the following tasks. An embodiment of the present invention will be described below with reference to the drawings.

First, the configuration of the front operation section 10 of the electronic cash register shown in FIG. 1 will be explained. In the figure, 11 is an amount key for calculating the amount of the product, 12 is a department key for specifying the department for each product, 13a is a correction key, 13b is a subtraction key, 1
3c is a key for temporarily saving data currently being registered or calling saved data; 13d is a key for specifying non-addition or exchange; 13e is a key for registering the person in charge number; 13f is a key for date and time data and the start time of aggregation by time zone. 13g is the product number key that presets the product number code in each department and time period aggregation register of the department key 12, 13M is the clear key, 14 is the credit for deposits, withdrawals, credits, etc. A key for each transaction instructs selling or lending, 15 is a subtotal key for calculating addition or total, and 16 is a key for calculating total or change and issuing a receipt. In addition, 17 is a mode switch, "OFF", "Setting ↓ "Registration", "Return ↓ "Inspection",
Switch and select each function of "Payment". The mode switch 17 is set to "OFF" when the cash register is not in use, and "registered" when performing normal money collection operations.
"Return" is used to cancel part of the money registered in the cash register, "Inspection" is used to remove the stored data without destroying it, "Payment" is used to clear the stored data after it has been read, and "Settings" is used to cancel part of the money registered in the cash register. Used to set preset data such as time and product number. Next, the system configuration of the present invention will be explained with reference to FIG.

21 in the figure is a CPU (central processing unit), and this CPU21
A memory circuit 22 and a clock circuit 23 are connected via a data bus DB for transferring data D, a row address bus RB for transferring row addresses RA, and a column address bus CB for transferring column addresses CA. The clock circuit 22 and the clock circuit 23 are each formed of an integrated circuit, and the chips are specified by the chip enable signals CE, CE2 sent from the CPU 21, and read/write by the read/write signal R/W2. Alternatively, writing is specified. Further, the CPU 21 is connected to the 1/1/2
0 boat 24 is connected. This 1/0 boat 24 is given an operation signal J from the CPU 21. This operation signal J is used to distinguish whether the signal sent from the CPU 21 via the column address bus CB is an address or a command. The 1/0 boat 24 has a key input section 25, a display section 26, and a printing section 27.
is connected. When the key input section 25 also performs a key operation, the timing signal KP from the 1/0 boat 24 is output.
Accordingly, the key input signal KI is input to an input buffer (not shown) in the 1/0 port 24. In addition, the display section 26
is the digit signal DG from the 1/0 boat 24 and the 1/0
A display operation is performed according to a segment signal SG obtained by decoding data in a display buffer (not shown) of the 0 port 24. The printing section 27 consists of, for example, a line printer,
The print position signal T of the print drum is sent to the 1/0 boat 24, and the hammer drive signal MD generated by the coincidence of this print position signal T and the data in the print buffer (not shown) of the 1/0 boat 24 is used. The hammer is driven to print on receipt paper and journal paper. Next, details of the CPU 21 will be explained with reference to FIG.

In the figure, numeral 31 is a control section in which various microinstructions are stored.

Then, the control unit 31 sends a signal SU that specifies the row address of the register storing the operands of the RAM 32, which is a memory for calculations to be described later, and a signal SU specifying the row address of the register storing the operands. Signal FU, signal SL that specifies the column address of the register that stores the operand or the processing start column address, signal FL that specifies the column address of the register that stores the operand or the processing end column address, and a numerical code. A signal C○, an operation code OP such as an arithmetic command or a transfer command, and a signal NA specifying its own next address are output in parallel via bus lines a to g, respectively. The signal NA output via the bus line g is temporarily stored in the buffer register 33 via the address conversion circuit 30. The output of the buffer register 33 is input to the address section 34. The address section 34 specifies the address of the control section 31 according to a signal input from the buffer register 33. Further, the operation code OP is supplied to the operation decoder 35 via the bus line f. The operation decoder 35 decodes the operation code OP and supplies it to the timing control circuit 36. This timing control circuit 36 sends a gate control signal to gate circuits 38, 39, etc. according to a command from an operation decoder 35 and a timing signal given from a timing signal generation circuit 37, and sends an up/down count command to a counter 40.
, a match detection command is output to the match circuit 41, an addition/subtraction command is output to the adder circuit 46, a judgment command is output to the address conversion circuit 30, and a proposal/write command R/W is output to the RAM 32. Furthermore, the read/write command R/W2 is sent to the memory circuit 22 and the clock circuit 23, and the operation signal J is sent to the memory circuit 22 and the clock circuit 23.
Output to 0 port 24. The row designation addresses SU and FU outputted from the control section 31 are applied to the gate circuit 38 via bus lines a and g, respectively, and the outputs of these gate circuits 38 are applied to the RA via the bus line h.
It is input to the row address input terminal UA of M32.

Further, the column address or processing start column designation address SL and the column address or processing end column designation address FL outputted from the RAM 32 from the control section 31 are applied to the gate circuit 39 via bus lines c and d, respectively. The output of the gate circuit 39 is outputted to the bus line i, inputted to the column address input terminal LA of the RAM 32, and outputted to the outside as a column address CA. Also,
The output of the gate circuit 39 is supplied to a counter 40. This counter 40 performs a counting operation based on a predetermined timing signal, and normally counts up by one each time a timing signal is input, but when a down-count command is given from the timing control circuit 36, Each time a timing signal is input, it counts down by one. Then, the output of the counter 40 is R
It is sent to the column address input terminal LA of AM32 and the above-mentioned outside, and is also applied to one input terminal of the matching circuit 41.
The other input terminal of the matching circuit 41 is given a processing end column designation address FL output from the control section 31 to the bus line d. The coincidence output of this coincidence circuit 41 is input to the timing control circuit 36. On the other hand, the RAM 32, which is the arithmetic memory, has a configuration as shown in FIG.
Addressed by the row address output by

Further, the digit is designated by the column designation address FL or SL, and the reading and writing are designated by the read/write command R/W output from the timing control circuit 36. Therefore, the operands and operands addressed by the row and column addresses, or the data output for transfer, etc., are output as parallel 4-bit data from the output terminal OD, and are sent to the gate circuit 42. The signal is sent to latch circuits 43 and 44 via the signal. The output of the latch circuit 43 is supplied to the input end b of the adder circuit 46 via the gate circuit 45 and is also sent to the buffer 47. This buffer 47 reads an input signal according to a predetermined timing signal, and its output is outputted to the outside as a row address RA. Further, the output of the latch circuit 44 is output to the data bus DB via the gate circuit 48, and is also applied to the input terminal a of the adder circuit 46 and a buffer 49 which performs an interrupt operation according to a predetermined timing signal. The data stored in this buffer 49 is decoded by the decoder 50, and the chip enable signal CE,
, CB2. When this chip enable signal CE is output, the memory circuit 22, CE
When 2 is output, the clock circuit 23 is connected to the CPU 21. Further, the carry signal outputted from the output terminal c of the adder circuit 46 is inputted to the address conversion circuit 30 together with the data taken out from the output terminal d of the adder circuit 46 via the OR circuit 51. Furthermore, the data output from the output terminal d of the adder circuit 46 is applied to the gate circuit 52 along with the data input from the outside via the data bus DB, and the output of this gate circuit 52 is applied to the data input terminal m of the RAM 32. added to. The gate circuit 52 and the gate circuits 38, 39, 42, 45, and 48 are controlled by a signal output from the timing control circuit 36. FIG. 4 is a configuration diagram of the RAM 32.

It consists of 4 lines and 2 lines, and the 0th line Accl is a calculation/display register, and the data entered by the calendar number using the key input section 25 is input to this Accl.

Acc2 is a calculation assisting register. Further, Acc3 is a register for transfer with the memory circuit 22.
Since it is not possible to perform arithmetic operations on the data within, the data is transferred to the RAM 32 and arithmetic operations are performed within the CPU 21. The ADC on the third row is an address counter, and its contents specify the row address of the memory circuit 22 via the row address bus RB.

CNT is a counter that counts the number of memories when registers of the memory circuit 22 are specified in order.
Further, HIN is an area for reading and storing a product number code from the product number code storage area of the memory circuit 22. K is a flag for determining the initial state when the product number code is preset in the memory for time period aggregation. On the other hand, the clock circuit 23
For example, the oscillation frequency of a crystal oscillator is divided to measure time, and the chip enable signal CE2 from the CPU 21
It is connected to the CPU 21 by.

Similarly, the CPU 21 issues a proposal/write command R/
W2 controls whether data (timekeeping information, ie, current time) is read to the CPU 21 or data (time data) is written from the CPU 21. The data storage area in the clock circuit 23 at that time is designated by the row address RA and column address CA from the CPU 21, and time data is exchanged via the data bus DB. FIG. 5 is a block diagram of the memory circuit 22 in FIG. 2.

Consisting of 31 lines and 2 lines, STM in the 0th line is a storage area for the start time of aggregation by time zone, T is a storage area for segmented time,
TM,,TM2. P and F are storage areas required for the time period aggregation operation.

Also, the 1st to 9th lines are the departmental total registers, 1819
The digit "20" is the program code indicating that this register is for departmental totals, and the 12th to 14th digits "101" ~
“108” is the product number code corresponding to departments 1 to 8. KOS is an area for storing the number of units sold in that department, and KIN is an area for storing the amount of sales. The 10th to 29th lines are registers for time period aggregation, "33" is the program code indicating that it is for time period aggregation, and TCD stores the sales of which product number department in the time period aggregation register. This is an area for storing a product number code indicating whether to total.

Note that "99" in the 18th and 19th lines of the 3rd column is a program code indicating that the time period total register ends here. The registers 1 to 3 above are called multipurpose memory, and can be used for various purposes by changing the program code. Next, the operation of this embodiment constructed as described above will be explained with reference to the flowcharts of FIGS. 6 to 9.

FIG. 6 shows a method of presetting data for time period aggregation. First, set the mode switch 17 shown in FIG. do.

Next, indicate the start time using four-digit hours and minutes. for example"
If we assume that the number of layers is ``601030'', this means that the data will be counted by time zone every 60 minutes starting at 10:30.
Then, when the date and time key 13f is pressed, the flow shown in FIG. 6 starts. In other words, the division time is 1/0 from the key input section 25.
T in the memory circuit 22 of the CPU 21 via the boat 24
, the start time is stored in the STM. FIG. 7 shows a method for presetting which product number is to be aggregated by time period. First, use the amount key 11 to directly enter the product number code, for example "101", and press the product number key 13g. The first register for counting by time period, that is, the 10th line of the memory circuit 22, is designated as the register for counting by time period for product number "101", and if the start time and division time are set according to the above preset example, then 30 at the time of one feeding. minutes to 11:03
Sales for the 60 minutes up to 0 minutes will be tallied this Regis evening.

Next, when the product number key 13g is pressed, the 11th line is designated. In other words, registers corresponding to the number of times the product number key 13g is pressed are prepared for counting product number "101" by time period. The flow shown in Fig. 7 starts with the operation of the product number key 13g, and at the first S, the flag K in the RAM 32 is initially "0", so it advances to S2, and the RAM
"n0" is set in the address counter ADC in 32. Since the address counter ADC specifies the row address of the memory circuit 22, the meaning of setting "10" is to specify the top row address "10" of the register for counting by time period.
10". S3 is the program code PC of the register specified by the address counter ADC
It is determined whether D is ``99'', and since ``99'' indicates that the register for counting by time period has ended, an error occurs. Set "K" on flag K at S4,
In S5, it is determined whether there is data in Accl of the RAM 32. This is to determine whether it is a product number key with the number of product number code replacements or a product number key without the number of layers, and the first time is
Since the number of layers is "101", the product number code in Accl is written to P of the memo IJ circuit 22 in S6. And P in S7
The contents of are transferred to the TCD of the register specified by the address counter ADC. However, the contents of P -WataruCPU2
After transferring it to RAM32 (for example, Acc3) in 1,
Needless to say, it is transferred to TCD. After the above operations are completed, the address counter ADC is incremented by 1 and the next operation of the product number key 13g is awaited. In this example, there are 20 registers for counting by time zone from 1st to 2nd, so let us assume that 16 of them are set for product number "101".

In other words, the 1st office is from 1 field: 30:30 to 11:30, the 11th office is from 11:30 to 12:30, and the 23rd office is from 1:30 to 11:30.
Sales from 1:30 p.m. to 2:30 p.m. are totaled. Next, the aggregation method of the present invention will be explained with reference to the flow shown in FIG.

The mode switch 17 is set to the registration position, and when there is a sale, the amount is counted using the amount key 11, and then the department key 12 to which the product number of the item belongs is pressed.

For example, if it is an item with the product number "101", the product number "101" is preset in the department 1, so the "01" key of the department wakiyama key 12 is pressed. Then, the flow shown in FIG. 8 starts. S.

Now, section 1, that is, 12 to 12 of the first row of the memory circuit 22.
Line 14: Preset product number code "101"
S, . are written in the area Hm of the RAM 32. ,S. At step 2, address counter ADC is set to "1" and CNT is set to "0". In S, 3, it is determined whether the program code of the register of the memory circuit 22 designated by the address counter ADC is 33, that is, whether it is a register for time period aggregation. As mentioned above, this register is a multi-purpose memory (memory that can be used for various purposes depending on the program).
The 1st to 2nd rows are Mochimori, and the 1st to 9th rows are divided by category.
A program code (PCD) is preset by a program for each of the 10 to 2 mochis to be counted by time period. Therefore, it is checked in order from the first address ``1'' of the multi-purpose memory whether or not the program code ``33'' for time period aggregation is preset. Here, the first line is PCD=20, and the process advances to S,4. S, 4
was created for the purpose of S3 and Oka, and the PCD is "99".
Otherwise, proceed to S, 5. and address counter AD
Count up C by 1 and return to S, 3. Next, we will look at the FCD on the second line. When the first position is reached in this way, PCD=33 is detected and the process proceeds to S, 6. In S,6, the contents of the TCD of that register are stored in RAM.
It is determined whether the contents match the contents of HIN No. 32 or not.
This is because even if it is a register for aggregation by time period, it is not known which product type is preset. If the code preset in the TCD of the time zone register and the code written in Hm at S, o do not match according to the flow shown in Fig. 6, the number is counted up at S, 5 and the next Start checking the register. Since it matches here,
Proceed to S, 7. From here, it is determined whether the current time is within the time zone set in the register. TM contains the upper limit of the time period set in that register, and T contains the lower limit. That is, when performing the operation of S,7, since CNT is "0", TM. contains STM contents. Next, after adding 1 to CNT at S, 8, the above ST is added to TM2 by the operation at S, 9.
The content of M plus the segment time T is included. S2
. Set flag F to "0" in S2, then T
Compare the contents of M and the current time. The current time is sent from the clock circuit 23 to the AC memory of the RAM 32 via the data bus DB.
It will be forwarded to c2. And the contents of TM, are Acc3
Acc2 and Acc3 are compared. If the current time is greater than TM, there is a possibility that the current time is within the time zone of that register, and the flag F is incremented by 1 in S22. Furthermore, in S23, the current time is changed to TM.
If it is smaller than 2, it is determined that the current time is in the time zone of that register, and flag F is set to "2" in S24.
shall be. Next, in S25, if it is determined that TM,>TM2, it means that the time period straddles two feeding times. For example, the 19;th register is set from 24:30 to 1:30, TM, is 2 ■ Horse 30 minutes, and TA
2 means 1 hour and 3 minutes. In this case, the flag F is incremented by 1 in S26, and a correction is made for the case where it is determined in S2 that TM>current time and S is not executed even though the current time is within that period. Therefore, only when the flag F is "2", the current time falls within the time zone of the register evening, and this is determined in S27, and if the flag F is not "2", the S. 5, the address counter ADC is incremented by 1 and the next register is specified.
When the flag F is "2", the number in Accl is added to the KOS of that register, and the amount is added to KIN, completing the registration of this product. By the way, recent electronic cash registers have a zero-skip function that does not print out the contents of the register if the contents of the register are "0" when printing out stored data at the time of inspection or payment. However, in an electronic cash register that performs time-based totals like the present invention, it is necessary to print out all the time-based total data without skipping zeros. This is because even if the contents of the register are "0", it is meaningful because it is information that there were no sales during that time period. Therefore, at the time of inspection or payment, the flow shown in FIG. 9 is executed. That is, S3. If the program code is "33", it is a register for counting by time zone, so it is printed out unconditionally. For registers whose program code is not "33", only those whose amount (KIN) and number (KOS) are "0" are not printed (zero skipped). In addition, in this example,
To simplify the explanation, only sales of items in department 1 were aggregated by time period, but it is also possible to aggregate sales by time period, such as by multiple departments, by person in charge, or by transaction. Also, if you create multiple start time storage areas and segment time storage areas, associate program codes with each, and query them every time you perform aggregation calculations, you can, for example, store sales by department and sales by manager in different time zones. It is possible to aggregate the information, or to aggregate the same department by multiple time periods. As described above, according to the present invention, the clock function is provided,
When processing sales, the time measured by the clock function described above is compared with the set time period, and various aggregation processes are performed for each set time period. Therefore, by simply setting the aggregation start time and segment time for each time period in advance, each time period can be calculated. A plurality of time slots can be automatically set for each time slot without setting the time for each slot, and sales can be totaled within each set time slot. Therefore, it is possible to know the sales status in each time period, and it is possible to create more detailed information such as changes in operators or replenishment of products, which can be extremely useful for management, etc. It has the following advantages.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention; FIG. 1 is a diagram showing the arrangement of keys on the front operation section, FIG. 2 is a system configuration diagram showing the overall circuit configuration, and FIG. 4 is a block diagram showing the details of the central processing unit (CPU) in the figure, FIG. 4 is a configuration diagram of the RAM in the CPU, FIG. 5 is a configuration diagram of the memory circuit in FIG. 2, and FIGS. 6 to 9 are 3 is a flowchart for explaining the operation of the present invention. 10...Operation unit, 21...CPU, 2
2...Memory circuit, 23...Clock circuit, 24...1/0 boat, STM...
Time period aggregation start time storage area, T.・・・・・・
Partitioned time storage. Figure 1 Figure N Boat chart Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9

Claims (1)

[Claims] 1. In an electronic cash register that performs various cumulative calculations on sales products, a clock circuit that measures the current time, a memory that stores the initial set start time and aggregation unit time of aggregation by time zone, and A calculation processing means for obtaining the actual time of the time period to be aggregated from the separate aggregation start time and the aggregation unit time, and a plurality of time periods set according to the plurality of time periods having the same time length obtained by the calculation processing means. a separate memory for aggregation; a determination means for determining whether or not the current time of the clock circuit falls within the above-mentioned real time during a registration operation; and a time period-specific aggregation memory corresponding to the result of this determination means. 1. A counting method in an electronic cash register, comprising means for selecting a memory and registering and tallying input data in the memory for counting by time period.