JPS6027476B2 - Time division digital communication device - Google Patents
Time division digital communication deviceInfo
- Publication number
- JPS6027476B2 JPS6027476B2 JP9894477A JP9894477A JPS6027476B2 JP S6027476 B2 JPS6027476 B2 JP S6027476B2 JP 9894477 A JP9894477 A JP 9894477A JP 9894477 A JP9894477 A JP 9894477A JP S6027476 B2 JPS6027476 B2 JP S6027476B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- exclusive
- subscriber
- output terminal
- common line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Small-Scale Networks (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Description
【発明の詳細な説明】
本発明は加入者間のデータ通信あるいは音声のディジタ
ル通話など通信をディジタル信号によって行なう時分割
ディジタル通信装魔に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time-division digital communication system in which communication such as data communication or digital voice communication between subscribers is performed using digital signals.
時分割ディジタル通信装置は通信路を多重使用して通信
を行なうが、従来の時分割ディジタル通信装置では送信
側加入者と受信側加入者とでは異なる時間を割り当てて
いる(以下この割りあてられた時間をタイムスロットと
称す)。従って、この装置では通話に関与する加入者が
同一共通線につながれてる場合、1つの通信に対しこの
共通線上で2タイムスロットを必要とするため通信の多
重度は共通線、即ち、通信路の多重度の1/2となる欠
点がある。本発明の目的は通信に関与する加入者が同一
共通線につながれている場合に1つの通信に対し1タイ
ムスロットのみを使用し通信の多重度を通話路の多重度
と等しくすることのできる時分割ディジタル通話装置を
提供することにある。Time-division digital communication equipment performs communication by multiplexing communication channels, but in conventional time-division digital communication equipment, different times are assigned to the sending subscriber and the receiving subscriber (hereinafter, this allocated time is time is called a time slot). Therefore, in this device, when subscribers involved in a call are connected to the same common line, two time slots are required on this common line for one communication, so the multiplicity of communication is limited to the common line, that is, the communication path. There is a drawback that the multiplicity is 1/2. An object of the present invention is to use only one time slot for one communication when subscribers involved in communication are connected to the same common line, and to make the multiplicity of communication equal to the multiplicity of the communication path. An object of the present invention is to provide a split digital communication device.
本発明の通信装置は、加入者回路の共通線側出力端子各
々につながれた複数の入力端子と複数の第1の排他論理
和回路とを有し前記入力端子の各々を前記複数の第1の
排他論理和回路のいずれか一つの入力端子に接続すると
共に前記の複数の第1の排他論理和回路を最終段が1個
の第1の排他論理和回路となるように多段接続し前記最
終段の第1の排他論理和回路の出力端子を出力端子とす
るように構成された論理回路と、前記論理回路の出力端
子と前記加入者回路の共通線入力端子全てとをつなぐ共
通線と、各加入者回路に設けられ前記加入者回路自身の
送信ディジタル信号と前記共通線により分配されるディ
ジタル信号とを入力され出力信号を加入者側に出力する
第2の排他論理和回路とから構成されている。The communication device of the present invention has a plurality of input terminals and a plurality of first exclusive OR circuits connected to each of the common line side output terminals of a subscriber circuit. the plurality of first exclusive OR circuits are connected in multiple stages such that the final stage is one first exclusive OR circuit, and the final stage is connected to any one input terminal of the exclusive OR circuit; a logic circuit configured to have the output terminal of the first exclusive OR circuit as an output terminal; a common line connecting the output terminal of the logic circuit to all the common line input terminals of the subscriber circuit; A second exclusive OR circuit is provided in the subscriber circuit and receives the transmitted digital signal of the subscriber circuit itself and the digital signal distributed by the common line, and outputs an output signal to the subscriber side. There is.
次に本発明を図面を用いて詳細に説明する。Next, the present invention will be explained in detail using the drawings.
第1図は本発明の一実施例を示すブロック図である。第
1図において、本発明の通信装置は、加入者回路1,2
,3,4及び5と、これら加入者回路の出力端子につな
がれた入力端子6,7,8,9及び10と、共通線17
によってこれら加入者回路の全ての入力端子につながれ
た出力様子16と、前記入力端子6,7を2つの入力と
する排他論理和回路12と、前記入力端子8,9を2つ
の入力とする排他論理和回路13と、排他論理和回路1
3の出力と前記入力端子10の入力とを2つの入力とす
る排他論理和回路14と、排他論理和回路12及び14
の出力を2つの入力とし出力が出力端子16に供給され
る排他論理和回路15を有する論理回路11とから構成
されている。FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, the communication device of the present invention includes subscriber circuits 1 and 2.
, 3, 4 and 5, input terminals 6, 7, 8, 9 and 10 connected to the output terminals of these subscriber circuits, and a common line 17.
An output circuit 16 connected to all the input terminals of these subscriber circuits, an exclusive OR circuit 12 having the input terminals 6 and 7 as two inputs, and an exclusive OR circuit 12 having the input terminals 8 and 9 as two inputs. OR circuit 13 and exclusive OR circuit 1
an exclusive OR circuit 14 whose two inputs are the output of 3 and the input of the input terminal 10; and exclusive OR circuits 12 and 14.
The logic circuit 11 has an exclusive OR circuit 15 whose output is supplied to an output terminal 16 and whose output is supplied to an output terminal 16.
なお、ここで述べる加入者回路とは音声のディジタル通
話装置においては、加入者からの2線信号を4線信号に
変換し帯域制限し、アナログーディジタル変換を行ない
得られたディジタル信号を出力するとともにディジタル
信号を入力され、ディジタルーァナログ変換を行ない得
られたアナログ信号を復調再生し2線信号に変換して加
入者に送出する回路あるいはデータ通信装置においては
送信側加入者端末装置からのデータ信号をディジタル信
号に変換し(例えば、標本化によりディジタル符号への
変換を行ない)出力するとともにディジタル信号を再生
して受信側加入者端末装置に送出する回路など、各加入
者に設けられ時分割でディジタル信号の入力及び出力を
行なう回路を意味する。第2図は本実施例に用いる加入
者回路を示す図である。In addition, the subscriber circuit described here is a circuit that converts a 2-wire signal from a subscriber into a 4-wire signal, limits the band, performs analog-to-digital conversion, and outputs the resulting digital signal in a voice digital communication device. In a circuit or data communication device that inputs a digital signal, performs digital-to-analog conversion, demodulates and regenerates the obtained analog signal, converts it into a two-wire signal, and sends it to the subscriber. Each subscriber is equipped with a circuit that converts the data signal into a digital signal (for example, converts it into a digital code through sampling) and outputs it, and also reproduces the digital signal and sends it to the receiving subscriber terminal. Refers to a circuit that inputs and outputs digital signals by dividing them. FIG. 2 is a diagram showing a subscriber circuit used in this embodiment.
第2図において、加入者回路18は、出力端子25と入
力端子26とを有し、変復調回路19と、変復調回路1
9の出力端子に一方の入力端子がつながれ出力端子が出
力端子25につながれた送信ゲート21と、一方の入力
端子が入力端子26につながれた受信ゲート22と、変
復調回路19の出力端子と受信ゲート22の出力端子と
に2つの入力端子がそれぞれつながれ出力端子が変復調
回路19の入力端子につながれた排他論理和回路20と
から構成されている。本装置を用いた加入者回路1及び
4の間の通信について説明する。In FIG. 2, the subscriber circuit 18 has an output terminal 25 and an input terminal 26, and a modulation/demodulation circuit 19 and a modulation/demodulation circuit 1.
A transmitting gate 21 whose one input terminal is connected to the output terminal of the modulation/demodulation circuit 19 and whose output terminal is connected to the output terminal 25, a receiving gate 22 whose one input terminal is connected to the input terminal 26, and the output terminal of the modulation/demodulation circuit 19 and the receiving gate 22, and an exclusive OR circuit 20 having two input terminals connected to each output terminal and an output terminal connected to an input terminal of a modulation/demodulation circuit 19. Communication between subscriber circuits 1 and 4 using this device will be explained.
加入者回路1及び4のそれぞれの変復調回路19に出力
されたディジタル信号A及びBは、両加入者回路の送信
ゲート21の1つの入力端子23にタイムスロットTで
ゲート信号を加えることにより両ゲートが開かれ、それ
ぞれの出力端子25に出力される。前記タイムスロット
Tで加入者回路1のディジタル信号Aは、入力端子6に
、加入者回路4のディジタル信号Bは入力端子9にそれ
ぞれ入力される。このとき、他の加入者回路2,3及び
5の送信ゲート21は閉じているので、入力端子7,8
及び10の論理レベルは“0”である。従って、排他論
理和回路12の出力信号はA、排他論理和回路13の出
力信号はBとなり、更に排他論理和回路14の出力信号
はBとなる。そして、排他論理和回路15の出力信号C
はA由B(=A・B+A・B)となり、出力端子16に
出力される。出力端子16に出力されたこのディジタル
信号Cは前記タイムスロットTで共通線17を介して各
加入者回路に分配される。加入者回路1においては、受
信ゲート22の入力端子24に前記タイムスロットTで
ゲート信号を加えることにより受信ゲート22が開かれ
前記ディジタル信号Cが入力される。排他論理和回路2
川ま、変復調回路19が出力したディジタル信号Aと論
理回路11より入力された前記ディジタル信号Cを入力
され、論理操作によってC由A=B、即ち、加入者回路
4のディジタル信号Bを復元し出力する。一方、加入者
回路4においても同様に前記タイムスロットTで前記デ
ィジタル信号Cを入力し、加入者回路1のディジタル信
号Aが復元される。第3図は本実施例に用いる論理回路
の別の例を示す図である。The digital signals A and B output to the respective modulation/demodulation circuits 19 of the subscriber circuits 1 and 4 are transmitted to both gates by applying a gate signal to one input terminal 23 of the transmission gate 21 of both subscriber circuits at time slot T. are opened and output to the respective output terminals 25. At the time slot T, the digital signal A of the subscriber circuit 1 is input to the input terminal 6, and the digital signal B of the subscriber circuit 4 is input to the input terminal 9. At this time, since the transmission gates 21 of the other subscriber circuits 2, 3, and 5 are closed, the input terminals 7, 8
The logic level of and 10 is "0". Therefore, the output signal of the exclusive OR circuit 12 is A, the output signal of the exclusive OR circuit 13 is B, and the output signal of the exclusive OR circuit 14 is B. Then, the output signal C of the exclusive OR circuit 15
becomes from A to B (=A.B+A.B), and is output to the output terminal 16. This digital signal C output to the output terminal 16 is distributed to each subscriber circuit via the common line 17 at the time slot T. In the subscriber circuit 1, by applying a gate signal to the input terminal 24 of the receiving gate 22 at the time slot T, the receiving gate 22 is opened and the digital signal C is input. Exclusive OR circuit 2
Kawama receives the digital signal A outputted by the modulation/demodulation circuit 19 and the digital signal C inputted from the logic circuit 11, and restores the digital signal B of the subscriber circuit 4 by logic operation so that A=B, that is, the digital signal B of the subscriber circuit 4. Output. On the other hand, the digital signal C is similarly input to the subscriber circuit 4 at the time slot T, and the digital signal A of the subscriber circuit 1 is restored. FIG. 3 is a diagram showing another example of the logic circuit used in this embodiment.
第3図において、論理回路27は、加入者回路の共通線
側出力端子につながれた入力端子32〜36と加入者回
路の共通線側入力端子すべてに共通線17を介しつなが
れた出力端子37とを有し、入力端子32及び33に2
つの入力端子がつながれた排他論理和回路28と、入力
端子34に一方の入力端子がつながれ排他論理和回路2
8の出力端子に他方の入力端子につながれた排他論理和
回路29と、入力端子35に一方の入力端子がつながれ
排他論理和回路29の出力端子に他方の入力端子がつな
がれた排他論理和回路30と、入力端子36に一方の入
力端子がつながれ排他論理和回路30の出力端子に他方
の入力端子がつながれ出力端子が前記出力端子37につ
ながれた排他論理和回路31とから構成されている。In FIG. 3, the logic circuit 27 has input terminals 32 to 36 connected to the common line side output terminal of the subscriber circuit, and an output terminal 37 connected to all the common line side input terminals of the subscriber circuit via the common line 17. 2 to the input terminals 32 and 33.
an exclusive OR circuit 28 with two input terminals connected to it, and an exclusive OR circuit 2 with one input terminal connected to the input terminal 34;
an exclusive OR circuit 29 whose output terminal is connected to the other input terminal, and an exclusive OR circuit 30 whose one input terminal is connected to the input terminal 35 and whose other input terminal is connected to the output terminal of the exclusive OR circuit 29. and an exclusive OR circuit 31 whose one input terminal is connected to the input terminal 36, the other input terminal is connected to the output terminal of the exclusive OR circuit 30, and whose output terminal is connected to the output terminal 37.
第4図は本実施例に用いる論理回路の更に別の例を示す
図である。FIG. 4 is a diagram showing still another example of the logic circuit used in this embodiment.
第4図において、論理回路38は、加入者回路の共通線
側出力端子につながれた入力端子43〜47と加入者回
路の共通線側入力端子全てに共通線17を介しつながれ
た出力端子48とを有し、入力端子43及び44及び入
力端子45及び46にそれぞれ2つの入力端子がつなが
れた排他論理和回路39及び40と、排他論理和回路3
9及び40の出力端子に2つの入力端子がつながれた排
他論理和回路41と、排他論理和回路41の出力端子に
一方の入力端子がつながれ入力端子47に他方の入力端
子がつながれ出力端子が前記出力端子48につながれた
排他論理和回路42とから構成されている。In FIG. 4, the logic circuit 38 has input terminals 43 to 47 connected to the common line side output terminal of the subscriber circuit, and an output terminal 48 connected to all the common line side input terminals of the subscriber circuit via the common line 17. Exclusive OR circuits 39 and 40 having two input terminals connected to input terminals 43 and 44 and input terminals 45 and 46, respectively, and exclusive OR circuit 3
An exclusive OR circuit 41 has two input terminals connected to the output terminals 9 and 40, one input terminal is connected to the output terminal of the exclusive OR circuit 41, the other input terminal is connected to the input terminal 47, and the output terminal is It consists of an exclusive OR circuit 42 connected to an output terminal 48.
このように本発明によれば1つのタイムスロットで双方
向の通信ができる。As described above, according to the present invention, bidirectional communication can be performed in one time slot.
本発明においては、従来の通信装置し、比べ共通線の多
重度が同じならば2倍の通信多重度が得られるため装置
を効率よく使用することができ装置の小型化・経済化に
大きな利益を有する。In the present invention, compared to conventional communication devices, if the multiplicity of the common line is the same, twice the communication multiplicity can be obtained, so the device can be used efficiently, and there is a great benefit in making the device smaller and more economical. has.
第1図は本発明の一実施例を示す図、第2図は本実施例
に用いる加入者回路、および第3図及び第4図は本実施
例に用いる論理回路の別の例を示す図である。
第1図〜第4図において、1〜5は加入者回路、11,
27及び38は論理回路、12〜15,20,28〜3
1及び39〜42は排他論理和回路、17は共通線、1
9は変復調回路、21,22はゲートを示す。
豹′図
豹そ図
第3図
第4図FIG. 1 is a diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing a subscriber circuit used in this embodiment, and FIGS. 3 and 4 are diagrams showing another example of a logic circuit used in this embodiment. It is. 1 to 4, 1 to 5 are subscriber circuits, 11,
27 and 38 are logic circuits, 12 to 15, 20, 28 to 3
1 and 39 to 42 are exclusive OR circuits, 17 is a common line, 1
Reference numeral 9 indicates a modulation/demodulation circuit, and 21 and 22 indicate gates. Leopard Figure Leopard Figure 3 Figure 4
Claims (1)
数の入力端子と複数の第1の排他論理和回路とを有し前
記入力端子の各々を前記複数の第1の排他論和回路のい
ずれか一つの入力端子に接続すると共に前記複数の第1
の排他論理和回路を最終段が1個の第1の排他論理和回
路となるように多段接続し前記最終段の第1の排他的論
理和回路の出力端子を出力端子とするように構成された
論理回路と、前記論理回路の出力端子と前記加入者回路
の出力端子と前記加入者回路の共通線側入力端子全てと
をつなぐ共通線と、各加入者回路に設けられ前記加入者
回路自身の送信デイジタル信号と前記共通線により分配
されるデイジタル信号とを入力され出力信号を加入者側
に出力する第2の排他論理和回路とから構成されたこと
を特徴とする時分割デイジタル通信装置。1 comprising a plurality of input terminals connected to each of the common line side output terminals of the subscriber circuit and a plurality of first exclusive OR circuits, each of the input terminals being connected to one of the plurality of first exclusive OR circuits; one of the plurality of input terminals and the plurality of first input terminals.
Exclusive OR circuits are connected in multiple stages such that the final stage is one first exclusive OR circuit, and the output terminal of the first exclusive OR circuit in the final stage is used as the output terminal. a common line connecting the output terminal of the logic circuit, the output terminal of the subscriber circuit, and all the common line side input terminals of the subscriber circuit; and a common line provided in each subscriber circuit that connects the subscriber circuit itself. and a second exclusive OR circuit which receives the transmitted digital signal and the digital signal distributed by the common line and outputs an output signal to the subscriber side.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9894477A JPS6027476B2 (en) | 1977-08-17 | 1977-08-17 | Time division digital communication device |
| US05/930,271 US4253179A (en) | 1977-08-17 | 1978-08-02 | Time division digital switching system with code converting and inverse-converting circuits |
| GB7832573A GB2002994B (en) | 1977-08-17 | 1978-08-08 | Time division digital switching system |
| SE7808591A SE433157B (en) | 1977-08-17 | 1978-08-11 | TIDDELNINGSDIGITALOMKOPPLINGSANORDNING |
| CA309,462A CA1110745A (en) | 1977-08-17 | 1978-08-16 | Time division digital switching system |
| FR7823899A FR2400802B1 (en) | 1977-08-17 | 1978-08-16 | TIME DIVISION DIGITAL SWITCHING DEVICE |
| DE2835756A DE2835756C2 (en) | 1977-08-17 | 1978-08-16 | Digital time division switching system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9894477A JPS6027476B2 (en) | 1977-08-17 | 1977-08-17 | Time division digital communication device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5432207A JPS5432207A (en) | 1979-03-09 |
| JPS6027476B2 true JPS6027476B2 (en) | 1985-06-28 |
Family
ID=14233205
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9894477A Expired JPS6027476B2 (en) | 1977-08-17 | 1977-08-17 | Time division digital communication device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6027476B2 (en) |
-
1977
- 1977-08-17 JP JP9894477A patent/JPS6027476B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5432207A (en) | 1979-03-09 |
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