JPS6027956B2 - How to output the day of the week on a digital clock - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for outputting days of the week in a digital clock. Conventional digital clocks carry out timekeeping operations by dividing a reference frequency in a counter.

That is, when using a commercial frequency (for example, 50Hz), first divide the frequency by 1/5 to count the seconds, then divide the seconds by 1/6 to count the minutes, and then divide the minutes by 1/6 again. The hour is divided by 1/12 to count the morning and afternoon, and finally the morning and afternoon are divided by 1/2 to count the day. Therefore, there are parts that can be displayed numerically, such as hours, minutes, and seconds, and parts that cannot be displayed numerically, such as morning and afternoon, and day and night. When this time is displayed on a figure-eight segment display tube, there is a drawback that the display of morning, afternoon and day of the week becomes extremely complicated. In other words, the segment display tube converts numerical information from 0 to 9 input in binary format into a, b, c, d, e, f,
It is necessary to convert the seven segments of g so that the numbers corresponding to the numerical information are lit. For example, when the numerical information is 1, a lighting pulse is output from the bc output terminal of the segment display decoder, and a mosaic display of 1 is performed on the segment display tube. Therefore, it was necessary to provide an additional driver circuit for the days of the week or morning/afternoon display portions where the aforementioned numeric display cannot be performed. The present invention has been made in view of the above-mentioned drawbacks, and provides a day-of-the-week output method for a digital clock in which both the time portion that can be displayed numerically and the day portion that cannot be displayed numerically can be operated by the same driver circuit.

Embodiments of the present invention will be described in detail below with reference to FIG. The present invention is applied to a digital clock in which the time and day of the week are output in chronological order from a counting section that performs a timekeeping operation by dividing a reference frequency. The above-mentioned digital timepiece is, for example, one having a counting section that is a combination of a shift register and a decoder, such as that disclosed in Tarukoshi No. 47-102965. Therefore, the counter of such a digital clock outputs the day of the week, morning, afternoon, hour, minute, and second at different timings. A feature of the present invention lies in the decoder and gate circuit.
That is, as shown in FIG. 2, there are a segment display decoder 1 and a day of the week display decoder 2. The segment display decoder 1 converts the time output from the counting section 6 into a signal for mosaic display of seven segments of abde bamboo, while the day of the week display decoder 2 converts the time output from the counting section 6 into a signal for mosaic display with seven segments of abde bamboo. is converted into a signal corresponding to each day of the week from 0 to 6. Therefore, if the output from the counter 6 is the time portion (hours, minutes, seconds), the segment display decoder 1 operates, and if the output is the day of the week, the day of the week display decoder 2 is operated, so switching is performed using a timing pulse. It will be done. Furthermore, the outputs of both decoders 1 and 2 are input to a timing gate circuit 3.

The timing gate circuit 3 includes two AND gate circuits 4,
4' and one OR gate circuit 5 are made up of seven sets. The output terminals 0 to 6 of the day of the week display decoder 2 and the day of the week output timing pulse ◇, are respectively input to one AND gate circuit 4 of each set, and the other AN
Output terminals a to g of the segment display decoder 1 and a time output timing pulse 2 are respectively input to the D gate circuit 4'. In addition, the outputs of both AND gate circuits are input to the next stage OR gate circuit, respectively A, B, etc.
G is taken out as output. With such a configuration, when the time is output from the counter 6, the segment display decoder 1 converts it into a signal for the segment display tube for mosaic display, and then the timing gate circuit 3 outputs a pulse signal.
2, signals exactly the same as the outputs a to g of the decoder 1 are outputted from the OR gate circuit 5 as A to G.

Next, when the day of the week is output from the counter 6, the day of the week display decoder 2 selects the day → 0. Moon → 1. Fire→2. Water → 3. Tree → 4
．． Gold → 5. A signal with a one-to-one correspondence like Sat→6 is output, and the timing gate circuit 3 generates a pulse? , synchronized with each day of the week, such as Sunday → 0 → A, Monday → 1 → B, Tuesday → 2 → C, Wednesday → 3 → D, Thursday → 4 → E, Friday → 5 → F, Saturday → 6 → G. A signal corresponding to the above is output from the OR gate circuits 5, 5, . . . . As described above, according to the present invention, there is an advantage that the output terminal for the time portion, which can display the day of the week but cannot be displayed numerically, can be shared. Therefore, the time can be displayed using a segment display tube using the outputs A to G of the timing gate circuit, and the day of the week can be displayed using a timing gate circuit using a display tube incorporating seven lamps corresponding to Sunday to Saturday or characters from day to ±. This can be done using the outputs A to G. Furthermore, the present invention
When converting to C, the day of the week,
Since the time can be displayed, it also has the secondary effect of reducing the number of IC output terminals by half. In addition to displaying the day of the week, the display of morning and afternoon can also be easily realized in the same manner as the day of the week by adding one more OR gate circuit to the morning and afternoon decoder and timing gate circuit.

[Brief explanation of the drawing]

FIG. 1 is a model plan view illustrating a known segment display tube, and FIG. 2 is a block diagram illustrating an embodiment of the present invention. 1 is a segment display decoder, 2 is a day of the week display decoder, 3 is a timing gate circuit, 4 and 4' are AND
A gate circuit, 5 is an OR gate circuit, and 6 is a calculation section. Figure 1 Figure 2

Claims (1)

[Claims] 1. In a digital clock in which the time and day of the week are output in chronological order from a counter, there is a time display decoder that converts the numerical information of the time into a time display signal, and a terminal from which the numerical information of the time is output. A day of the week display decoder that converts the day of the week information retrieved in time series into a day of the week display signal is provided in parallel, and each output of the time display decoder and the day of the week display decoder is controlled by a timing signal. A digital clock characterized in that the output terminals of the time and day of the week display signals are shared by applying the voltage to a timing gate circuit and outputting the output signals of the respective decoders at different timings from the output of the timing gate circuit. Day of the week output method.