JPS6028171B2 - Code/decoding circuit using ROM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention reduces the circuit scale by using a block code decoding circuit used in digital transmission, especially ROM (read-on memory), and operates using a large amount of synchronization information. This invention relates to a word synchronization circuit designed to stabilize

AM1 (bipolar) codes, which are easy to code convert, have no DC component, and are easy to detect errors, are widely put into practical use as transmission line codes for digital transmission systems. However, A.M.
Since the I code is a code that only alternately distributes logical 1's into 10's and 1's (logical 0 remains unchanged), if logical 0's continue, the clock used for code inversion cannot be recovered on the receiving side. In addition, the information efficiency is not good, so for these reasons, codes that are rich in timing information, have few DC components, and have good information efficiency are being considered recently. One of them is m
There is a block code in which a bit binary code is converted into an n-digit L-value code according to a predetermined conversion rule. By utilizing its redundancy, this block code can enrich timing information, reduce DC components, and even enable false detection, but the biggest drawback is that This requires a word synchronization circuit that roughly divides the code into n digits in synchronization with the transmitting side.
This will be explained using the MS43 equal sign as an example. - The MS43 code is a block code that converts a 4-bit binary code into a 3-digit ternary code according to the conversion rules shown in Table 1 below. Table 1 In the method shown above, three ternary encoding modes A, B, and C are prepared for one block of binary code, and these are selected by RDS.

RDS (Running digi PISum) is the algebraic sum (addition of logic + as 11, logic 0 as 0, and logic - as -1) from the past to the present of ternary codes that are sequentially converted and output. If it is an integral method, it will be an integral value. When RDS=+1, mode A is selected. Similarly, when RDS=+2 or 13, mode B is
When S=14, mode C is selected. For example, if the RDS up to the previous block is 11 and the next input binary code is 0000, the mode is A, so the output ternary code is converted to 110. For such MS4 milk equal sign, ■ RDS takes only four values from 11 to 14, ■ RDS uses ternary code + 10, 110, 10 10, 0 10. = 11, and the ternary code 111 110, 101, 01- is used only when RDS = +4. ■ There is no ternary code of 000. By using these characteristics, it is possible to determine whether word synchronization is correct or abnormal.

However, if a word synchronization circuit that utilizes all of ■~■ is constructed using normal individual components, the circuit configuration will become large-scale, so generally, a word synchronization circuit is configured using only a portion of ■~■. are doing. FIG. 1 shows a word synchronization circuit (the entire circuit is a code/decoder circuit) that utilizes only the property (2) above.

In the figure, 1 is a decoder, and the input ternary code MS43
The 10th side and the 1st side are separated and output to the serial/parallel converter circuit 2. 0
and those of opposite polarity are both set to 0.

In this way, the input ternary code of n bits becomes a serial binary code of phantom bits. For example, if the ternary code MS43 is 011, the output on the tenth side of the decoder will be a binary code 010, which is 1 only at the tenth digit among the three digits, and the output on the one side will be one only at the -digit among the three digits. 0
It becomes 01. The serial-to-parallel conversion circuit 2 takes in 6 bits of each serial output from the decoder 1 and converts it into a parallel binary code D.
, ~D6. In the above code example, D, ~D6
becomes 010001. This acquisition of each 6 bits is 1
This is done by the output of /3 dividing circuit 7. The code conversion circuit 3 converts codes D, to DB into 4-bit parallel 2
Convert back to value data. At this time, the integral value RDS is used. 4 is a parallel-to-serial conversion circuit;
Converts bit parallel output to 4 bit serial output.

This 4-bit binary data is retimed by the frequency clock CLK in the flip-flop 5, subjected to noise removal, etc., and taken into a subsequent stage circuit (not shown). Next, to explain the timing relationship, the timing circuit 6
extracts the clock component from block code MS43.

Since the block code MS43 is a 4-bit binary code converted into 3 digits without changing the time length of one block, if the frequency of the basic clock of the binary code is fo, then the output frequency of the timing circuit 6 is becomes go/4.
This is used in the decoder 1 and also in the frequency divider circuit 7.
The frequency is divided by /3. The output (chi/4) of the frequency dividing circuit 7 is S/
It is used in the P conversion circuit 2 and is multiplied by 4 in the multiplier circuit 8. 3 is a circuit that extracts the clock CLK of frequency fo from the output of the multiplier circuit 8, and the output thereof is supplied to the flip-flop 5, and is reduced to 1/4 again by the 1/4 frequency divider circuit 10 for P/S conversion. It is supplied to circuit 4.

In order for code inverse conversion to be performed correctly in such a code decoding circuit, the 200 million serial codes on each side of 10 and 1 that are taken in by the S/P conversion circuit 2 must be synchronized with the transmitting side and correctly converted into 3 codes on each of 10 and 1. need to be separated.

Since the output (fo/4) of the frequency dividing circuit 7 indicates this division, its generation timing (phase) is important, and the word synchronization circuit 11 appropriately corrects this phase (establishes word synchronization). The word synchronization circuit 11 is equipped with an integral value counter that calculates RDS from codes D, ~D6, and an out-of-synchronization detection circuit. An abnormal pulse is generated when However, since this abnormal pulse is also generated by a simple code error on the transmission path, a protection circuit 12 is provided, and the circuit causes the frequency dividing circuit 7 to correct the output phase by one step only when the abnormal pulse occurs several times in a row. The read synchronization control pulse Pc is sent out. The word synchronization circuit 11 in FIG. 1 utilizes only the above-mentioned feature (2) of the MS43 equal sign in order not to increase the circuit scale.

However, even if word synchronization is lost, RDS does not necessarily take values outside the range of 11 to 14, and during that time
Phenomena that violate these conditions may also occur. Therefore, in a word synchronization circuit that uses only a part of the above ■ to ■ in order to reduce the circuit scale, the word synchronization loss detection will be delayed accordingly.
The synchronization pull-in time including the protection time becomes long and the operation becomes unstable. The present invention attempts to stabilize word synchronization by making maximum use of the features of code conversion rules without increasing the circuit scale.

A code decoding circuit that receives and decodes a block code string obtained by converting an m-bit binary code into an n-digit L-value code according to a predetermined conversion rule converts the received block code string into a binary code in units of blocks. An m-bit parallel binary code which receives the converted and serial-parallel converted code and the previous RDS value obtained by delaying the RDS value outputted by itself as an address, and inversely converts the block code string, Abnormal bits indicating loss of synchronization or code error, normal bits indicating no loss of synchronization or code error, and the RD
The first ROM that outputs the S value and the normal bit and abnormal bit are input, and it has a counter function and when an abnormal bit is input while word synchronization is normal, it increases the count value and keeps it constant. and a second ROM that generates an output for moving the dividing line position in units of blocks to achieve word synchronization when the value exceeds the value, and this will be described in detail below with reference to the illustrated embodiment. explain. Second
The figure is a block diagram showing one embodiment of the present invention, and the same parts as in FIG. 1 are given the same reference numerals.

This example also inversely converts the MS43 equal sign as in FIG. 1, but the code conversion circuit 3 and word synchronization circuit 11 in FIG.
and a portion corresponding to the protection circuit 12 is stored in two ROM1
3 and 14 are different. The input of the first ROM 13 is 8 bits. ~D6 is S/P conversion circuit 2-6
A bit-parallel code is provided. T,, T2 is the integral value RD
This is a 2-bit code corresponding to S, which is obtained by delaying each of the outputs T3 and T4 by 1 bit by the delay circuit 15. The output of the ROM 13 is also 8 bits, ○7 to 0, o are 4-bit parallel binary data outputs that have been reversely code-converted, E is a control output that becomes 1 when synchronization is lost or a code error occurs, and R is a code that changes even when synchronization is lost. This is a control output that is 1 when there is no error and normal operation. Third
The figure is a conceptual diagram of ROM 13, 16 is a code conversion table,
17 is a normal/abnormal discrimination table; 18 is an integral value table.

These tables 16 to 18 all have inputs D, to D6.
, T, , T2 are addresses A, ~A8. The code conversion table 16 inversely converts the 6-bit data D, .about.6 into 4-bit data D7-D, o according to the mode specified by the contents (RDS values) of the inputs T, . In other words, T
,,T2 is RDS=+1 to 14, which are each represented by 2-bit codes 00, 01, 10, and 11, so T2 is
,, If T2 is 00, then the data D, ~D
6 is inversely transformed according to mode A of Table 1. As mentioned above, if the data is D,~D6a010001, it means ternary data 0~, so if reverse conversion is performed according to Table 1, D7~D,o becomes 1011. Specifically, write to table 16 so that when addresses A, ~A8 are 01000100, 1011 will be output to outputs D7~D, o, and do the same thing for all combinations in Table 1. I'll keep it. The integral value table 18 has inputs D, to D6
The polarity sum for one block of MS43 equal signs (maximum is 13 of 110 to minimum of -3 of ---) is calculated from the previous R
The DS values, that is, T, and L, are added to be used as the next RDS values, that is, T3 and T4.

Specifically, the inputs D, ~D6, T, , L are set to addresses A, ~
As A8, necessary data is written so that the output corresponding to the above addition operation is read out at T3. For example, if T, , T2 are RDS values +1 (00 in binary code) and D, to D6 are 010001, then D. ~ D6 no Hara 3
Since the polarity sum of the value code 011 is 0, the RDS value 11 (binary code 00) is output again at T3 and T4. The normal/abnormality determination table 17 uses all of the above-mentioned characteristics ① to ① of the MS43 code to discriminate between normal and abnormalities.

In other words, {a} When the MS4 milk equal sign is 000, this is a pattern that cannot exist under normal conditions, so B = 1 (abnormal)
becomes. That is, if D, to D6 are 000000, E=1 is output from the table 17. This takes advantage of feature (■). 'b' At the same time, feature (2) is used to compare and monitor the facultative sum, that is, the mode, and the structure of the MS43 code. For example, when input D, ~D6 is 111000, that is, 110 in the MS4 group equal sign, if T,, T2 is other than 00 (mode A), 110 is only in mode A, so it is a bit error or out of period. I understand. Furthermore, as is clear from Table 1, the MS4*equal sign having a polarity sum of absolute value 2 or 3 exists only in mode A and mode C, so this is used to perform error determination. This is summarized in Table 2. Table 2 For example, when the polarity sum is -3, that is, in MS34, T
,,T2 should be 11, that is, 4, and originally T3,
T4 should be 1, more specifically 00, but since it is not 1, this means that an MS34 code that is not in the selected mode has been input, and there is concern about bit errors or loss of synchronization.

Therefore, E=1, so R=0, and T3 and T4 are set to the correct value of 1. When the polarity sum is -2, the mode should be C, and T3, T4=2 is correct, but if not, E=1 and T3, T4 are changed to 2. The same applies below. The upper half of the above table shows that the polarity sum of the input MS43 code is -
Public in 3, 12, 12, 13. RDS value of L is 11, 12
, 13, or 14, it is abnormal, so set E=1 in Table 17, and also change the RDS values of T3 and T4 in Table 18 to 11 (12, 13, 14). And, in the lower half, the polarity sum of the input MS43 equal sign is -3
, 12, 12, 13, and the RDS values of T3 and T4 are 11, 12, 13, and 14, which is normal, so R= for table 17.
It means to set it to 1. The second ROM 14 has a function of setting forward and backward protection times.

Since E=1 in the first ROM 13 is also output in response to a code error on the transmission path, the counter function of the ROM 14 is used to distinguish this from out-of-synchronization. The inputs of the ROM14 are E, R, S,,P,,...Pn, and the outputs are A, S2, P',,...P'n, and if both the input and output are 8 bits, Since P, .about.Pn, P', .about.P'n are 5 bits, about 30 steps of protection time can be set for both forward and backward. If about 7 stages of forward and backward protection are sufficient, a ROM with 6 bits of input and 5 bits of output will be sufficient, and the circuit scale will be further reduced. Outputs P', -Pn are each inputted to input P. through a 1-bit delay circuit 15. ~Pn, and the input P.~Pn is read out using the input P, ~Pn as an address. ~
A value 1 greater than Pn is read out at output P', .about.Pn. This counter operation is controlled by inputs E and R. Input S
, is the output S2 delayed by 1 bit, and S,=0 indicates that word synchronization is normal;
,=1 indicates a state in which word synchronization is determined to be abnormal.
The word synchronization control pulse Pc for the frequency dividing circuit 7 is the output A
appears in Next, the operation will be explained.

In this case as well, basically a specific storage area is addressed and the information previously written there is retrieved, but the following description will be made in the same way as a general counting circuit. [11
S,: When 0 (normal): Each time E=1, the number indicated by the outputs P', .about.Pn is increased by 1.

If R=1 appears during this time, the output P′, ~P
Reset n. If E = 1 occurs frequently and R = 1 does not appear during that time, P', ~Pn will simply increase, so when it exceeds a certain amount (forward protection level), a pulse Pc is output to output A, and at the same time Reset P', .about.Pn. As a result, the phase of the output fo/4 of the frequency dividing circuit 7 is corrected by one step. As a result, the position of the dividing line that divides the input serial code into three codes moves back by one code, and the constituent members of the code to be blocked change. If word synchronization is not established even after this phase correction, the above-described operation is repeated. [2} When S2=1 (abnormal): Every time R=1, the number indicated by the output P', ~P'n is changed to 1.
Increase by increments.

If E=1 appears during this time, then P′, ~P′n
is reset, and a control pulse Pc is output from output A at the same time. If R=1 occurs frequently and E=1 does not appear during that time, P
', .about.P'n simply increase, so when it exceeds a certain value (backward protection), it is assumed that the synchronization pull-in is completed, and S2 is reset to 0 and P', .about.Pn are reset. still,
As mentioned above, when a transmission path error occurs, E=1 as shown in the upper half of Table 2, so if you output 1 to another bit in response to this, it will cause an error in the transmission path. It shows.

Furthermore, the present invention can be applied not only to MS43 codes but also to other integral value control codes, and further to mode alternating codes such as common control codes. FIG. 4 is a block diagram showing a main part of another embodiment of the present invention applied to the decoding of a unipolar code. In this example, the wave pattern converts a 2-bit 1-block binary code into 3-bit 2-bit 2-bit code according to a predetermined conversion rule.
Since it is converted into a value code, the output of the S/P conversion circuit 2 becomes a 3-bit parallel binary code D, to D3. These codes D, ~D3 are inversely converted into 2-bit parallel binary data D4, D5 (
decoding), but the point that the ROMs 13 and 14 constitute a word synchronization circuit is the same as in FIG. 2 (the delay circuit is omitted in the drawing). As described above, according to the present invention,
Since the word synchronization circuit can be constructed only by using a ROM, word synchronization can be controlled by making maximum use of the characteristic points of each transmission line code conversion without increasing the circuit scale.

Therefore, there are many opportunities to detect out-of-word synchronization, and the detection is quick, and the synchronization recovery time is shortened, so stable decoding operation can be expected.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an example of a conventional MS4 group equal code decoding circuit, Figure 2 is a block diagram showing an embodiment of the present invention applied to MS43 equal code, and Figure 3 is for code conversion and error detection. FIG. 4 is an explanatory diagram of the ROM of FIG. 4, and FIG. This is a diagram. In the figure, 13 and 14 are ROMs forming a code conversion circuit and a word synchronization circuit. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1 In a code decoding circuit that receives and decodes a block code string obtained by converting an m-bit binary code into an n-digit L-value code according to a predetermined conversion rule, the received block code string is converted into a binary code in block units. and the previous RSD value obtained by delaying the RDS value output by itself are input as addresses,
A first ROM that outputs an m-bit parallel binary code obtained by inversely converting the block code string, abnormal bits indicating out-of-sync or code errors, normal bits indicating no out-of-sync or code errors, and the RDS value. Then, when the normal bit and the abnormal bit are input, and the word synchronization is assumed to be normal due to the counter function, if an abnormal bit is input, the counted value is increased, and when it exceeds a certain value, the block unit division is performed. a second ROM that generates an output for moving the line position and achieving word synchronization.
Code/decoding circuit using OM.