JPS6028454B2 - Scramble method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a scrambling method that prevents erroneous synchronization due to a pattern identical to a frame pulse pattern included in a scramble pattern having a period equal to the frame period.

In digital wireless communication devices such as PCM communication systems, scrambling is performed for the purpose of spreading the frequency spectrum of transmitted energy. This is to prevent the occurrence of spike-like components in the transmission spectrum and to facilitate the extraction of clock components on the receiving side. There are two types of scrambling: an asynchronous type that performs scrambling regardless of the frame period, and a synchronous type that performs scrambling in synchronization with the frame period. is targeted at.

FIG. 1 is an explanatory diagram showing an example of a frame structure of a multiplexed signal.

In the figure, F,, F2, F3, . . . , FM indicate frame pulses, and D,, D2, D3, . Also F,,D
,, F2, D2, .
For the frame pulses F,, F2, F3, . . . FM, a pseudorandom signal with a period M is normally used. FIG. 2 is a circuit diagram showing the configuration of the scrambling circuit.

In the figure, reference numeral 1 denotes a multiplexing circuit that multiplexes a main signal input and a frame pulse input to generate a framed multiplexed signal as shown in FIG. 2 is a scramble pattern generator which generates a scramble pattern consisting of a pseudo-random signal.

Reference numeral 3 is an EX-OR circuit which performs exclusive OR of the multiplexed signal and the scramble pattern to generate a scrambled output signal.

The receiving side is equipped with a scrambling pattern generator that generates the same scrambling pattern as that on the transmitting side, and the pseudo-random signal is removed from the received signal by exclusive ORing the received signal and the scramble pattern. The original multiplexed signal can be recovered.

Now, in the scrambling circuit as shown in Fig. 2, when performing synchronous scrambling on the frame structure as shown in Fig. 1, the subframe period is (
When performing scrambling with a pseudo-random signal of N+1) bits, the main signal is disconnected (all “0” or all “1”).
), the output signal becomes the scramble pattern itself or its inverted signal, and the remaining periodicity becomes a problem.On the other hand, when main signal interruption is detected, a pseudo-random signal is used instead of the main signal. An input method has been proposed.

In this case, the above-mentioned problem does not occur, but on the other hand, there is a drawback that the amount of hardware increases. On the other hand, the longer the length of the scramble pattern, the less the periodicity remains as described above.

Therefore, it is conceivable to perform scrambling using a pseudo-random signal of one frame length instead of subframes.
In this case, the length of the scramble pattern is one frame length, that is, (N+1)×M bits, so randomness is increased and residual periodicity is decreased. however,
In this case, the following problems arise. In the frame configuration shown in FIG. 1, frame pulses F,, F2,
F3, . . . , FM are composed of pseudo-random signals.

If the input signal is cut off and the scramble pattern or its inverted signal is sent out from the scrambling circuit, the frame synchronization circuit on the receiving side will not synchronize with the frame pulses F,, F2, F3, ..., FM. , a phenomenon occurs in which the frame pulse pattern coincides with the same pattern included in the scramble pattern or its inverted signal. The present invention attempts to eliminate such drawbacks of the prior art, and its purpose is to provide a periodic scrambling method that uses a scrambled pattern having a period equal to the frame period. The object of the present invention is to provide a method that prevents false synchronization by removing patterns that are the same as the frame pulse patterns contained in the frame pulse pattern.

To achieve this objective, in the scrambling method of the present invention, a multiplexed signal in which a frame is constructed by arranging a plurality of subframes each consisting of a frame pulse and a plurality of data bits in series has a period equal to the frame period. A scrambling circuit that performs scrambling using a scrambling pattern includes means for detecting at least some bits of a pattern identical to a frame pulse pattern included in the scrambling pattern at the same period as a frame pulse; the scrambling is performed using the changed scrambling pattern; In a scrambling circuit that performs scrambling on a multiplexed signal composed of a frame pulse pattern using a scramble pattern having a period equal to the frame period, a memory that stores a scramble pattern that does not include a pattern that is the same as the frame pulse pattern, and a memory that stores a scramble pattern that does not include the same pattern as the frame pulse pattern, and a and an address counter that generates an address signal for reading the contents of the memory, and scrambling is performed using a scramble pattern read from the memory. Hereinafter, the present invention will be explained in detail based on the drawings.

FIG. 3 is an explanatory diagram showing the principle of the present invention.

In the same figure, A indicates a scramble pattern generator,
Q, , Q2, Q, and Q4 are D type flip-flops, and G is an EX-OR circuit. In addition, B indicates each signal, Bo is a flip-flop, amplifier Q,,Q2,Q,Q4
, Co is a scramble pulse, Do is a frame pulse pattern, and Eo is a sampling output. In FIG. 3, a case is shown in which M=5 and N=2 in the frame structure shown in FIG. 1, and therefore one frame in this case is composed of 15 bits.

Also, frame pulse patterns F, . F2,...
It is assumed that F5 is 10100. In FIG. 3A, flip-flops Q, , Q2, Q3, and Q4 have their Q outputs and D inputs successively connected in cascade, and are connected to flip-flops Q3, Q3, and Q4 by EX-OR circuits, respectively.
A pseudorandom signal is generated by calculating the exclusive OR of each Q output of Q4 and feeding back the operation result to the D input of the flip-flop Q. In FIG. 3B, B indicates the logic state of each Q output of each flip-flop Q, , Q2, Q, Q for clock periods 1 and 5 with the same symbols. The pseudorandom signal uses the Q output of the flip-flop Q and is composed of 15 bits. In the scrambling circuit shown in FIG. 2, no scrambling is performed on frame pulses.

Therefore, in the pseudo-random signal shown in FIG. 3B, a signal is created in which every 3 bits are set to "0" to form a scramble pattern. In FIG. 3B, Co indicates the scramble pattern thus generated, and Do indicates the aforementioned frame pulse pattern, with each pulse corresponding to the aforementioned "0" in the scramble pattern. The scramble pattern thus created and its inverted signal are sampled at the same period as the frame pulse.

However, since scrambling is not performed on the frame pulse portion as described above, there is no need to perform sampling. In FIG. 3B, Eo indicates the sampling output, 1 is the sampling output shown in comparison with the scrambled pattern, and 2 is the sampling output shown in comparison with the inverted signal of the scrambled pattern. It shows. Now, looking at these sampling outputs, 1
Of the outputs shown in , the second bits 3, 6, 9, 12, from the frame pulse in the scramble pattern
The sampled output for 15) is the same as the frame pulse pattern starting from the 7th bit.

Therefore, when the scramble pattern shown in Co of FIG. 3B is used, there is a possibility that synchronization will occur on the receiving side when the input is interrupted. Therefore, the scramble pattern is changed so that it does not include the same pattern as such a frame pulse pattern.

As an example, the 15th bit in the scramble pattern shown in Co in FIG. 3B may be changed from "0" to "1". In addition to changing the sign of only one bit, there are other ways to change the sign of all bits of the same pattern as the frame pulse pattern (for example, 3, 6, 9, 12, 1
How to set the 5th bit) to “1” or how to set all bits to “1”
Various methods can be considered, such as changing the pulse pattern to 0''. In other words, it is sufficient that the change results in a pattern different from the frame pulse pattern.
As is clear from the configuration of the scrambling circuit shown in Figure 2, sampling is also performed on the inverted signal of the scrambled pattern by simply performing exclusive OR with the multiplexed signal. This is because if the main signal is cut off, the multiplexed signal does not necessarily become "0", but may become "1".

FIG. 4 is a circuit diagram showing the configuration of an embodiment of the scrambling method of the present invention.

In the figure, the same parts as in Figure 3 are indicated by the same numbers, and G2, ○3, G4, G5, and G6 are NAND circuits
7 and G8 are AND circuits, and G9 is an OR circuit. In FIG. 4, flip-flops Q, , Q2, Q, Q and EX-OR circuits constitute the same scramble pattern generator as in FIG. 3A.

NAND circuits G2, G3, G4, G5, and G6 output "0" when they detect the combination of outputs of flip-flops Q, Q2, Q, and Q that correspond to bits that should be set to "0" in the scramble pattern. . Note that such combinations of flip-flop outputs are shown at K in FIG. 3B corresponding to clock periods 1, 4, 7, 10, and 13. AND circuit G7 is the Q of flip-flop Q4.
The logical product of the output and each output of NAND circuits ○2, G3, G4, G5, and OB is calculated. Therefore, a scramble pattern indicated by Co in FIG. 3B is produced at its output. On the other hand, the AND circuit G8 changes "0" to "1" to make it different from the frame pulse pattern.
A combination of the outputs of flip-flops Q, Q2, Q3, and Q4 corresponding to the first consecutive bit in the scramble pattern is detected to generate ``1''.

AND circuit G in OR circuit 09? , G8, a scramble pattern in which the outputs are changed as required is obtained. FIG. 5 is a circuit diagram showing the configuration of a second embodiment of the scrambling method of the present invention.

In this figure, the same parts as in FIG. 4 are indicated by the same numbers, G, o are NAND circuits, G, . is an AND circuit. Figure 5 shows one bit “1” in the scramble pattern.
In this case, the 12th bit in the scramble pattern shown in Co in Figure 3B is changed to "0".
This example shows the case where The NAND circuits ○, o detect the combination of the outputs of the flip-flops Q, , Q2, Q, Q corresponding to the 12th bit in the scramble pattern and generate "0". NAND circuit C. The output of is "1" at other times, and the AND circuit ○, . By calculating the logical product of the outputs of the AND circuit G7 and the NAND circuits G and o, a scramble pattern is generated in which the output is changed as required. It goes without saying that the sign of the inverted signal of the scramble pattern can be changed in exactly the same manner.

Further, the above-mentioned scramble pattern can be generated in advance and stored in a memo, and read out from the memory and used as necessary.

FIG. 6 is a circuit diagram showing the configuration of a third embodiment of the scrambling method of the present invention.

In the figure, 11 is a memory, and 12 is an address counter. In FIG. 6, the memory 11 is
A scramble pattern generated by means such as the embodiment shown in the figure is stored. address counter 1
2 generates an address signal for the memory 1 in response to a clock signal input, whereby the scramble pattern stored in the memory 11 is read out and a desired output is generated. The scramble signal generated in this way is applied from the scramble pattern generator to the EX-OR in the scrambling circuit shown in FIG.
It is exclusive-ORed with the multiplexed signal in the circuit to generate a scrambled output signal. As explained above, according to the scrambling method of the present invention, in a synchronous scramble method using a scrambling pattern having a period equal to the frame period, the same pattern as the frame pulse pattern included in the scramble pattern or its inverted signal can be used. This is extremely effective because it can prevent erroneous synchronization due to

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing an example of the frame structure of a multiplexed signal, FIG. 2 is a circuit diagram showing the structure of a scrambling circuit,
FIG. 3 is an explanatory diagram showing the principle of the scrambling method of the present invention, and FIGS. 4, 5, and 6 are circuit diagrams each showing the configuration of an embodiment of the scrambling method of the present invention. 1... Multiplexing circuit, 2... Scramble pattern generator, 3... EX-OR circuit, 11...
・Memory, 12...Address counter, Q,,Q2,Q
, Q...○ type flip-flop, G. ...EX-O
R circuit, G2, G3, G4, G5, G6, G,. ...NAND circuit, G7, G8, G, .・・・・
・AND circuit, G9...OR circuit. Figure 1 Figure 2 Figure 3 Figure 6 Figure 4 Figure 5

Claims (1)

[Claims] A multiplexed signal in which a frame is constructed by arranging a plurality of subframes each consisting of a frame pulse and a plurality of data bits in series is scrambled by a scrambling pattern having a cycle equal to the frame cycle. In the scrambling circuit, the scrambling circuit includes means for detecting at least some bits of the same pattern as a frame pulse pattern included in the scrambling pattern at the same period as the frame pulse, and changing the bits detected by the detecting means. 1. A scrambling method, comprising: means for performing scrambling using the changed scrambling pattern. 2. In a scrambling circuit for scrambling a multiplexed signal in which a frame is constructed by arranging a plurality of subframes each consisting of a frame pulse and a plurality of data bits in series, using a scrambling pattern having a period equal to the frame period. , a memory for storing a scramble pattern that does not include a pattern identical to a frame pulse pattern, and an address counter that generates an address signal for reading out the contents of the memory in response to a clock signal, the scramble pattern being read from the memory. A scrambling method characterized by performing scrambling using.