JPS6029070B2 - rotation speed detector - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital rotational speed detector in which an encoder is attached to a rotating shaft.

In recent years, digital rotation speed detectors have been increasingly used in place of analog systems such as speed generators, but the most typical one is a voltage signal obtained by F/V converting the output pulse train from an encoder. There are methods such as integrating clock pulses over a fixed sample period or reciprocal calculation using a rate multi-element.
The former method that integrates pulses has a problem with instantaneous response, and the latter reciprocal calculation method has a complicated circuit, lacks precision, and requires digital switching.

The present invention relates to a rotational speed detector using an encoder, and is an object of the present invention to solve the above-mentioned various problems and provide a speed detector with a quick response time and a simple structure.

FIGS. 1 and 2 show time charts and graphs for explaining the principle of the present invention.

The time chart in Figure 1 shows that I is the encoder output and the period is T.
It has a tooth waveform of 1 and provides N teeth portions per rotation. The figure shows a clock waveform consisting of a pulse train at a target frequency. From these waveforms, the rotational speed V [rpm], the encoder output N pieces [pieces/period], and the clock frequency [Hz]
, the relationship between the clock count number Nx is found as T=,/
vessel xN=etc.・・・．・・・． ...'1) Therefore, the difference between the rotational speed V and the clock count number Nx during the encoder output period T is V's i//Poison x N-Plexus side--
-...[21 holds true.

The graph in Figure 2 shows the formula ■, with the rotational speed V [rpm] on the vertical axis and the clock count number Nx on the horizontal axis. For example, if you count Nx = A, you can find V = B. The rotational speed V.sub.2 can be read from the Nx-V table in which the clock count number Nx is written in the address and the rotational speed V in the data. However, this N
In the case of the x-V table calculation method, at the 4th point of the rotational speed V■ where the detected speed is low (e.g. point Q in Figure 2), the rate of change of the rotational speed V with respect to the increase in the clock count number Nx 4. As a matter of course, this tendency becomes more severe as the rotational speed V becomes smaller and the clock count number Nx increases, and the memory capacity becomes enormous. That is, in FIG. 2, the maximum distance Vw of the rotational speed V
・MAX=Vo's address N×o, the deviation of V that changes when N× increases by 1 bit.・・・・・・・・・【3'
If you want to make the error 8 with respect to the full scale of V 0.1% or less, the necessary value of Nxo is △V<〇. 〇.

IXV. Stand x 60 x (death N death;) Mi.

・0.1XV.

．．・・・． ...'4}V.

Shayanagi Xshi Nxo>999
・・・・・・・・・It can be calculated as '5'.

Therefore, if Nxo is set to 1000 and V is set to 2047~1, the Vo of V■・MAX is 2M7=special×. poison. . X6
0......[Represented by 61, so when V is 1, Nx is Nx: 2047 x 1000
......{7}.

That is, in order to suppress the reading error to 0.1% for a 1-bit displacement of Nx in the range of 2047 to 1 for V, 21×20
It requires 47K memory capacity, which is 2K P-
This corresponds to more than 2,000 ROMs, which is impossible to realize. In view of the above, in the present invention, V is given to the address and Nx is written to the data section.
To explain using the Nx characteristic diagram, the maximum value V of the rotational speed V
If o corresponds to 2047 bits, the weight of 1 bit on the vertical axis becomes Vo/2047 (detection error is 0.05%), and the value of the axis Nx corresponding to the change point for each bit on the vertical axis, for example, the speed V ■(N), V's (N11), V■(N+
2) Count number Nx(N), Nx(N
+1), Nx (N +12)......, and set the above V's (N), V's (N) to the P-ROM address.
11),...... and write Nx(N), Nx(
N11), ...... are written, and the clock count number Nx becomes the write count number Nx(N), Nx(N+
1), Nx(N+2). Each time the clock count reaches 1 bit, the P-ROM address is incremented by 1 bit, and the clock count number Nx(N+...
) of the speed signal V (N+...
).

FIG. 4 shows a block diagram of the embodiment.

In the figure, 1 is a P-ROM, and the rotation speed V is taken as the address, and the corresponding clock count number Nx is written in the data section. 2 is a comparator and the output of the addition counter 3 which counts the clock count number Nx and the above P-R.
When the OMI write data matches, a match signal is output. 4 is a subtraction counter that repeatedly subtracts one bit from the set value (for example, 2047) corresponding to the maximum rotational speed Vo every time the coincidence signal output occurs, and calculates the number of subtracted bits from the rising edge of the encoder output to the next rising edge, that is, The residual subtraction counter value each time becomes clear and the instantaneous rotational speed V
get the.

Reference numeral 5 denotes an output register which latches the instantaneous rotational speed V obtained by the subtraction counter 4 in response to a data acquisition command corresponding to the rise timing of the encoder output.

Reference numeral 6 denotes a timing pulse generation circuit which receives an encoder output signal and a clock signal to control the entire system, and outputs a clear signal and a load signal to the addition counter 3 and subtraction counter 4, as well as a command to take in data to the output register 5.

Further, 7 is a frequency dividing circuit, and 8 is an AND gate. In other words, the address of P-ROMI is (N) of rotation speed V, V
■(N+・), V's (N+2)...... is given, Nx(N), Nx(N+1), Nx(N+2),...
. . . is written in advance, and the output of the addition counter 3, which counts the period T of the tooth waveform from the encoder (not shown) separately from the clock signal, becomes the write data Nx (N ), NX (N11), NX (N+2
), ......, a match output is generated from the comparator 2, and this match output is added to the subtraction counter 4, which subtracts 1 bit from the maximum value (2047) of the child setting, and calculates the P-ROMI. The address is incremented, and this operation is continued until the timing of the next rising signal of the encoder output, and finally the value of the remaining subtraction counter 4 becomes the desired rotational speed V.

Therefore, it is only necessary to take in this V at the output register 5, and a data take-in command is issued in response to the rising edge of the encoder output, and the data latch is completed. When this data latch is completed, a clear signal for rear force top calculation counter 3 and a load signal for subtraction counter 4 are issued, and addition counter 3 is cleared to the drop value, and subtraction counter 4 is set to the maximum value ( 2047) and enters into a preparation state to count between the teeth of the next encoder output. After a while, the tooth waveform period T of the encoder output
is calculated instantaneously each time, and Nx- is calculated in advance.
The rotational speed V can be easily determined using the V' reciprocal number table, and since the obtained rotational speed V is an instantaneous value, for example, the state of speed fluctuation in a transient state can be very clearly seen.

In the above embodiment, the clock count number corresponding to the rotational speed Vm is written as it is as the write data in the memory, but in order to reduce the memory capacity, the difference in the clock count number corresponding to the disassembly of the rotational speed Vm is written. A clock count number corresponding to the speed difference between the rotational speeds V (N) and V (N+1) may be written.

As described above, the present invention relates to a method of determining the rotational speed from the period T of the encoder output using a reciprocal table, and the writing to the memory address and the data section is reversed, the address corresponds to the rotational speed, and the data section is written to the current rotation speed. The clock count number corresponding to the speed is written, and the response speed can be said to be almost instantaneous for each tooth waveform of the encoder output, and in terms of accuracy, if the subtraction counter is set to 11 bits, the P-ROM becomes the town byte, and 1 address is 1
/2047, which is less than 0.05%, and if it is 12 bits, P-ROM is 4K bytes, and one address is equivalent to 1/4095, which is less than 0.025%, and by using several ICs. Extremely high accuracy such as 0.05% or 0.025% can be obtained, and the detection speed range is also high-speed ROM if the encoder output is 1500 teeth/round.
When in use, it can measure up to about 400 KHz, or 1600 pm, and if it is a P-ROM, it can measure up to 90 kHz, or 360 pm, and the scale is linear rather than logarithmic, so there is no need to change the scale. It has excellent features such as:

[Brief explanation of the drawing]

1 and 2 are time charts and graphs for explaining the principle of the present invention, FIG. 3 is a -Nx characteristic diagram of V according to the present invention, and FIG. 4 is a block diagram of an embodiment. 1... Memory, 2... Comparator, 3... Addition counter, 4... Subtraction counter, 5... Output register. , 'Picture 2 Picture Spear 3 Picture Said 4 Picture

Claims (1)

[Scope of Claims] 1. In a rotational speed detector that uses a clock frequency to count the teeth waveform period from an encoder connected to a rotating body to be detected and calculates the rotational speed by taking the reciprocal, the address of the memory is made to correspond to the rotational speed. The clock count number of the tooth waveform period corresponding to the rotation speed is written in the data section, and the clock count number of the tooth waveform period from the encoder by the addition counter is compared with the written data in the memory using a comparator. A coincidence output is generated every time the rotation speed is set to the maximum value, and the subtraction is repeated for 1 bit for each coincidence output, and the address in the memory mentioned above is incremented. A rotational speed detector characterized in that the value of a subtraction counter that continues until the next rising edge of the teeth waveform and finally remains is read out as the rotational speed. 2. The rotational speed detector according to claim 1, wherein the clock count difference corresponding to the rotational speed resolution is written in the memory data section to reduce the memory capacity.