JPS6029242B2 - Bias circuit module - Google Patents
Bias circuit moduleInfo
- Publication number
- JPS6029242B2 JPS6029242B2 JP16478878A JP16478878A JPS6029242B2 JP S6029242 B2 JPS6029242 B2 JP S6029242B2 JP 16478878 A JP16478878 A JP 16478878A JP 16478878 A JP16478878 A JP 16478878A JP S6029242 B2 JPS6029242 B2 JP S6029242B2
- Authority
- JP
- Japan
- Prior art keywords
- bias circuit
- circuit module
- capacitor
- layer
- inductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Waveguides (AREA)
- Filters And Equalizers (AREA)
- Control Of Motors That Do Not Use Commutators (AREA)
Description
【発明の詳細な説明】
本発明は超小型マイクロ波用バイアス回路モジュールに
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a micromicrowave bias circuit module.
マイクロ波増幅器に使用されるバイアス回路は第１図に
示すようにィンダクタＬ、キャパシタＣ、抵抗Ｒによっ
て構成される。A bias circuit used in a microwave amplifier is composed of an inductor L, a capacitor C, and a resistor R, as shown in FIG.
比等の構成要素は具体的には、例えばＬ＝１価日，Ｃ＝
３５０のＦ，Ｒこ５００といった値である。此等のうち
ＬとＲについては薄膜によって形成する場合、特に寸法
的に問題となることはないが、Ｃだけは比較的大容量で
あって、バイアス回路モジュールの４・型化にとって一
つの隣路となっている。本発明はキャパシタの平板電極
を利用し、その上にＬ，Ｒを形成することによってこの
問題を解決したバイアス回路モジュールを提供するもの
である。Specifically, the components such as ratios are, for example, L = monovalent day, C =
The values are 350 F, R and 500. Of these, when L and R are formed using thin films, there is no particular problem in terms of dimensions, but C has a relatively large capacity and is one of the adjacent components for making the bias circuit module 4-inch. It is a road. The present invention provides a bias circuit module that solves this problem by using a flat plate electrode of a capacitor and forming L and R on it.
本発明の実施例を第２図に示す。An embodiment of the invention is shown in FIG.
１は低抵抗シリコン基板で、その上にキャパシタの下方
の金属電極２、誘電体層３及び上方の金属電極４が被着
形成されている。Reference numeral 1 denotes a low-resistance silicon substrate, on which are deposited a lower metal electrode 2, a dielectric layer 3, and an upper metal electrode 4 of the capacitor.
このキャパシタの電極は例えば０．８肋×０．８側程度
の寸法であり、より大きな溶量を必要とする場合には積
層型に形成してもよい。その場合電極板の接続は、極板
の端部の必要な部分を露出させ、接続用金属を被着する
ことによって行うことができる。このように形成したキ
ャパシタの上方の電極４の上に５〜ｌｏＡｍ程度にポリ
ィミド樹脂を塗布し、その上に皮膜抵抗６とインダクタ
７を形成する。The electrodes of this capacitor have dimensions of, for example, about 0.8 ribs x 0.8 sides, and may be formed in a laminated type if a larger amount of melt is required. In that case, the electrode plates can be connected by exposing the necessary portions of the ends of the electrode plates and applying a connecting metal. Polyimide resin is applied to a thickness of about 5 to 10 Am on the electrode 4 above the capacitor thus formed, and a film resistor 6 and an inductor 7 are formed thereon.
このィンダクタは電極面積をほぼ一杯に使えば１０ター
ン程度のコイルとすることによって所要のィンダクタス
を得ることができる。此等のＬ，Ｒと、キャパシタの上
方電極４との接続はポリィミド樹脂層を選択的に除去し
て孔８をあげ、その側壁に金を葵着したのち、選択メッ
キで金層の厚さを増してやればよい。This inductor can obtain the required inductance by forming a coil with about 10 turns if the electrode area is used almost to its full potential. To connect these L and R to the upper electrode 4 of the capacitor, the polyimide resin layer is selectively removed to form a hole 8, gold is deposited on the side wall of the hole 8, and then gold is deposited on the side wall of the hole 8, and then the thickness of the gold layer is adjusted by selective plating. All you have to do is increase it.
実作業の手順としてはポリィミドの開孔を先行させ、蒸
着した金層で開孔の側壁に導体層を設けると共に、コイ
ルをフオトプロセスによって形成することになる。The actual procedure is to first open a hole in the polyimide, provide a conductor layer on the side wall of the hole using a vapor-deposited gold layer, and then form a coil using a photo process.
本発明の構造をとることによって超小型バイアス回路モ
ジュールが実現する。By adopting the structure of the present invention, an ultra-small bias circuit module is realized.
第１図はバイアス回路を示す図、第２図は本発明のモジ
ュールを示す図であって、１は固体基板、２，４はキャ
パシタの電極、３は誘電体、５はポリィミド樹脂、６は
抵抗体、７はィンダクタ、８は閥孔である。
第１図
第２図FIG. 1 is a diagram showing a bias circuit, and FIG. 2 is a diagram showing a module of the present invention, in which 1 is a solid substrate, 2 and 4 are capacitor electrodes, 3 is a dielectric, 5 is a polyimide resin, and 6 is a diagram showing a module of the present invention. A resistor, 7 an inductor, and 8 a hole. Figure 1 Figure 2
Claims (1)
られてキヤパシタを構成し、該キヤパシタの上部電極層
上に絶縁体層が設けられ、該絶縁体層上に皮膜状の抵抗
体及びインダクタが形成されており、前記キヤパシタの
上部電極層と、前記抵抗体及びインダクタとは前記絶縁
体層に設けられた開孔を通して接続されていることを特
徴とするマイクロ波用バイアス回路モジユール。1. An upper electrode layer is provided on the lower electrode layer via a dielectric layer to form a capacitor, an insulator layer is provided on the upper electrode layer of the capacitor, and a film-like resistor is provided on the insulator layer. and an inductor are formed, and the upper electrode layer of the capacitor, the resistor and the inductor are connected through an opening provided in the insulator layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16478878A JPS6029242B2 (en) | 1978-12-28 | 1978-12-28 | Bias circuit module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16478878A JPS6029242B2 (en) | 1978-12-28 | 1978-12-28 | Bias circuit module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5591850A JPS5591850A (en) | 1980-07-11 |
| JPS6029242B2 true JPS6029242B2 (en) | 1985-07-09 |
Family
ID=15799948
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16478878A Expired JPS6029242B2 (en) | 1978-12-28 | 1978-12-28 | Bias circuit module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6029242B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5843542A (en) * | 1981-09-08 | 1983-03-14 | Fujitsu Ltd | Microwave integrated circuit |
| JPS5869947U (en) * | 1981-11-06 | 1983-05-12 | 三菱電機株式会社 | microwave semiconductor circuit |
| US5760456A (en) * | 1995-12-21 | 1998-06-02 | Grzegorek; Andrew Z. | Integrated circuit compatible planar inductors with increased Q |
| JP2758889B2 (en) * | 1996-07-12 | 1998-05-28 | 福島日本電気株式会社 | 1-chip low-pass filter |
| JP3159196B2 (en) * | 1999-02-04 | 2001-04-23 | 株式会社村田製作所 | Variable inductance element |
-
1978
- 1978-12-28 JP JP16478878A patent/JPS6029242B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5591850A (en) | 1980-07-11 |
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