JPS6029406B2 - Arithmetic control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic control system, and more particularly to an adder system with large propagation delays due to printed patterns.

In information processing devices that require high-speed processing capability, the most common method for improving processing speed is to maximize the length of data that can be processed within one machine cycle.

A typical high-speed processing device processes data width of approximately 8 bytes in one machine cycle. Now, when considering a binary look-ahead adder, if you compare a 4-byte wide adder and an 8-byte wide adder, the difference in the number of gate stages between the two is about 1 or 2 stages, Conventionally, as far as adders are concerned, the difference in gate delay is not that large.

By the way, in recent years, due to advances in highly integrated semiconductor technology, the speed per gate stage has improved dramatically.
Propagation delays caused by printed patterns that communicate between semiconductor devices have become extremely important in the machine cycles of processing equipment. When comparing a 4-byte adder and an 8-byte adder, the former only needs to transmit a carry from the least significant bit to the upper 31 bits, while the latter only needs to transmit a carry from the least significant bit to the upper 63 bits. It is necessary to transmit the delay time between semiconductor elements for the carry propagation due to the latter, which is inevitably larger than the former and becomes zero.

Further, in the conventional processing device, since only one set of adders is provided, four arithmetic operation instructions are controlled by one set of adders, and the number of data paths to be input to the adder increases.

Therefore, when attempting to realize a logic device using an actual semiconductor integrated circuit, physical constraints are imposed on the input/output pins of the semiconductor integrated circuit, and each element must be placed in isolation.

Therefore, in order to free ourselves from these physical constraints and improve the processing capacity of the device, we installed multiple computing units.
A method is used in which a group of instructions to be processed is assigned to each arithmetic unit.

FIG. 1 is an explanatory diagram of a functionally distributed arithmetic unit including a plurality of arithmetic units.

In FIG. 1, an arithmetic unit 1 is divided into a first arithmetic unit (hereinafter referred to as 1 unit) 2 and a second arithmetic unit (hereinafter referred to as G unit) 3.

The F unit 2 executes floating point instructions and fixed point multiplication/division, and the G unit 3 executes fixed point addition/subtraction, logical operations, single-point operations, privileged instructions, interrupt processing, and the like. The split configuration shown in Figure 1 increases the amount of hardware for the entire device, but since each calculation unit 2 and 3 is designed to improve functionality in its own field of expertise, the processing capacity of the entire device can be increased. can be raised. That is, in the case of FIG. 1, G unit 3
The adder in F unit 2 performs fixed-point addition and subtraction, 1G star operations, and logical operations, whereas the adder in F unit 2 only needs to have the function to perform binary addition and subtraction, and can execute floating-point instructions and multiplication and division. Therefore, it is sufficient to configure the adder considering only binary addition and subtraction, and the amount of hardware required is smaller than that of the adder of the G unit 3.

On the other hand, the adder in G unit 3 requires more types of operations than the adder in F unit 2, but since instructions that result in an operation loop such as multiplication and division are performed in F unit 2, In unit 3, it is possible to set the time taken within one machine cycle of the adder to be long.

Next, when focusing on the input data to the arithmetic unit 1, the F unit 2 must prepare general-purpose registers, floating-point registers, storage, and interfaces for inputting the first and second operands of floating-point instructions and multiplication/division instructions. In contrast, in the G unit 3, in addition to data input of the two operands of a general instruction, in order to process privileged instructions, etc., the G unit 3 inputs control information within the device (program status word, contents of control registers, etc.) There are many resources that need to be communicated within the device, such as sending channel addresses for input and output channels.

Therefore, in Gunit 3, as mentioned above, the semiconductor integrated circuit is subject to physical constraints on the number of input/output pins, which makes it difficult to place the upper and lower bit positions of the adder close to each other due to implementation. . In this way, the adder in G unit 3 in the configuration shown in FIG. Since there are many units, it is difficult to arrange them closer to each other than the F unit 2 in terms of mounting.

Therefore, it becomes difficult to perform a carry within a predetermined time within one machine cycle. An object of the present invention is to solve such problems by reducing the processing performance within the machine cycle of the device when it is difficult to transmit the carry of the adder within a predetermined machine cycle. Without,
The object of the present invention is to provide an arithmetic control method for performing addition and subtraction.

The arithmetic control method of the present invention consists of an upper adder that calculates the upper part of an input data length and a lower adder that calculates the lower part. a first flip-flop that holds the carry to the higher order generated in the adder; a second flip-flop that supplies the carry of the first flip-flop to the upper adder in the next cycle;
a flip-flop, and a condition determining means that operates at the time of a comparison instruction and determines by inputting the equality in the upper adder, the presence or absence of a carry, and the equality in the lower adder, and the presence or absence of a carry, respectively. However, in the case of an addition instruction, after inputting the lower part in the first cycle and adding it in the lower adder, in the second cycle, inputting the higher part and adding it in the upper adder, and in the case of a comparison command, the upper and lower The characteristic is that the condition determination means performs a subtraction operation at the same time, and the condition determination means determines the carry without propagating the carry from the lower to the upper.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram of an adder according to the present invention.

Hereinafter, for convenience of explanation, it is assumed that the basic data width is 8 bytes.

X register 4 and Y register 5 are each 8-byte registers and serve as the X-side input and Y-side input to the adder.

Note that both the X-side input register 4 and the Y-side input register 5 are 1.
Although each input line has one input line, each input line may have a plurality of input lines. Additionally, the adder 6 inputs the upper 4 bytes of the X register 4 and the upper 4 bytes of the Y register 5, and
The adder 7 is a high-order adder that performs byte addition, and the adder 7 is a low-order adder that inputs the lower 4 bytes of the X register 4 and the lower 4 bytes of the Y register 5 and performs 4-byte addition. Output registers 8 and 9 that store the calculation results of adders 6 and 7 can return the calculation results to X register 4 or Y register 5 via signal line 104. Also, “Flip
Flop 1 stores the carry from the most significant bit of the lower four bytes, and flip-flop 11 is a delay flip-flop that transmits the lower carry to the upper carry when adding or subtracting 8 bytes. Furthermore, the condition determination unit 12 determines the result of subtraction using a comparison instruction. Note that the X register 4 and Y register 5 are connected to an appropriate data path in order to transfer data with a general-purpose register or storage device, or with other arithmetic units in the arithmetic unit such as a shifter. Although it is provided, it is omitted because it is not directly related. Second
In the figure, adders 6 and 7 are added from × register 4 and Y register 5.
After the data input to the adders 6 and 7 perform the necessary operations, the data is processed by one machine before returning from the signal line 104 to the X register 4 and Y register 5 via the output registers 8 and 9. - Cycles are assigned.

The adders 6 and 7 have functions of performing logical operations such as logical sum, logical product, and exclusive logical sum, and addition and subtraction of binary numbers or the number of 1G ships.

The most time-consuming signal transmission in an adder is the carry transmission from the least significant bit to the most significant bit, but logic operations do not require signal transmission between the upper and lower bits, so gates The number of steps is small, and it can be executed in a shorter time than addition and subtraction. Therefore, in the adder shown in Fig. 2, it is divided into two, adder 6 for the upper 4 bytes and adder 7 for the lower 4 bytes, and in order to perform addition and subtraction of 8 bytes, the adder for the lower 4 bytes must be added in the first cycle. and add the upper 4 bytes in the next cycle to obtain the 8-byte addition result in 2 cycles, which alleviates the time constraints of the adder with respect to machine cycles and at the same time reduces the actual performance. In order to prevent this, implement the following method for logical operations, comparison instructions, and continuous operations.

That is, for logical operations, 8-byte processing is executed in one machine cycle, and for comparison instructions, 8-byte input data is compared and carry is transmitted from the lower 4 bytes to the upper 4 bytes. The comparison result is calculated in one machine cycle without any processing, and for continuous operations, the upper 4 bytes and lower 4 bytes are calculated continuously in one machine cycle.
By doing so in pitch, the performance degradation is limited to an increase of one machine cycle compared to an 8-byte adder.
These logical operations, 8-byte addition/subtraction, comparison instruction processing, and continuous operation will be explained with reference to FIGS. 3 to 6.

In FIG. 2, when 8-byte input data and 8-byte input data are set in X register 4 and Y register 5, when adders 6 and 7 are requested to perform a logical operation,
Since adders 6 and 7 do not transmit carry, one machine/machine
Completes an 8-byte logical operation within a cycle. FIG. 3 is a time chart of logical operation operations in FIG. 2.

One machine cycle of the device is divided into time pulses to to t3, and the data input to the X register (X-REG) 4 and the Y register (Y-REG) 5 are simultaneously added to adders 6 and 7. Then, the calculation results are set in the timer output registers (01REG) 8 and 9, and then the data is returned to the X register 4 and Y register 5 via the signal line 104, so one machine cycle (the E in figure 3
An 8-byte logical operation is performed in o).

FIG. 4 is a time chart of the 8-byte addition/subtraction operations in FIG.

When 8 bytes of input data are input to the X register 4 and Y register 5 at the beginning of the Eo cycle, the operation result of the lower 4 bytes is first transferred to the lower 4 byte output register (0-REG( L)) is set to 9, and at the same time the carry from the lower 04 bytes to the upper one is set in the flip-flop FFIO.

The contents of flip-flop 10 are transferred to flip-flop FFI I at time to, and the contents of flip-flop 10 are transferred to the next E. At cycle time ', the upper 4 bytes of the input X register 4, the upper 4 bytes of the input Y register 5, and the contents of the carry flip-flop FFII from the lower
Byte addition result is output register (0-REG(U))
Set to 8. In this way, the output upper 4 byte register (01 REG (U)
)8 and output lower 4 bytes. Register (01 REG (L)
) 9 is set, and the 8-byte addition/subtraction is completed by transferring the operation result to the X register 4 and the Y register 5 at time to at the end of the cycle. FIG. 5 is a detailed block diagram of the condition determination section of the comparison instruction in FIG. 2.

When comparing two 8-byte operands, if the contents of the X register 4 and Y register 5 are x-REG and Y-REG, the condition determining section determines the following conditions and sets a condition code.

×-REG=Y-REG X-REG<Y-REG},. ．． ．． ．． ．． '1,X-RE
When a G>Y-REG comparison instruction is requested, adders 6 and 7
subtracts Y-REG from X-REG, but this 8-byte subtraction completes in one machine cycle.

Normally, the comparison instruction does not require the operation result, and the operation result is carried from the top of the operation result and all the operation results are
Only the information as to whether it is J or not is required. Therefore, when executing the comparison instruction, "1" is forcibly added to the carry to the upper 4-byte adder 6 to take the two's complement of the Y input, regardless of the flip-flop 11, and the operation ends. Sometimes, the result of operation for the upper four bytes, ignoring the carry from the lower byte, is set in the upper output register.

Now, when considering the size judgment within the range of the upper 4 bytes, the upper 4 bytes of × register 4 are
U), upper 4 bytes of Y register 5 as Y-REG(U)
Then, if x-REG(U)=Y-REG(U), the result of subtraction is "0", and x-REG(U}
In the case of <Y-REG(U), the subtraction result is not "0" and the carry from the top of the subtraction result is "0", and ), each can be determined based on the fact that the carry from the top of the subtraction result is "1".

Now, when comparing 8 bytes, adders 6 and 7 independently subtract the upper 4 bytes and lower 4 bytes.
), or if ×1 REG (U) × Y-REG (U) can be determined, the comparison result of the two operands can be obtained only from the determination result of the upper 4 bytes, regardless of the operation result of the lower 4 bytes. It is clear that

On the other hand, if the subtraction result of the upper 4 bytes is "0",
Just because the upper 4 bytes of register Y 4 and Y register 5 are exactly the same, the entire 8-byte data is
- The relationship is determined by the subtraction result of the lower 4 bytes.

In FIG. 5, the signal line 104 becomes "1" when the operation results of the upper 4 bytes are all "0";
5 is the operation result of the upper 4 bytes, which becomes "1" when there is a carry from the most significant bit to the upper order, and the signal line 106 becomes "1" when the lower 4 bytes of the adder 7 are all "0".
Therefore, the signal line 107 is "1" when there is a carry from the lower 4 bytes to the upper one, that is, the flip-flop 10
is connected to. In FIG. 5, ×-REG=Y-
In the case of REG, the signal lines 104 and 106 are connected to the AND circuit 19
By inputting the signal line 108 to "IJ",
In the case of 1REG<Y-REG, if the upper 4 bytes are equal, the AND circuit 18 sets the signal line 110 to "1", and if the upper 4 bytes are equal, the AND circuit 21 sets the signal line 110 to "1" through the OR circuit 23, and then X-REG> Y-REG
In this case, if the upper 4 bytes are not equal, the AND circuit 17
Also, if the upper 4 bytes are equal, the AND circuit 20
' From this, the signal line 109 becomes "1" through the OR circuit 22.
becomes.

By providing the condition determining section 12 with such a configuration,
When executing a comparison instruction, it is possible to perform an 8-byte comparison in one machine cycle by ignoring the "carrier 1" from the lower 4 bytes to the upper 4 bytes and subtracting each 4 byte independently. It becomes possible.

Next, the continuous addition operation, which is the third feature of the present invention, is
This will be explained using figures.

In the present invention, normally two machine cycles are required to obtain an 8-byte addition result, but as in the case of continuous addition of X=X0Y, the addition result of the previous cycle is transferred to the next In continuous operations where new additions are made in cycles, 8
Compared to an adder that can add bytes in one cycle, it is possible to perform continuous operations with only one cycle of deterioration in loop performance.

If the calculation loop of X=X+Y competes n times, the final result ×
is expressed by the following equation, where F is the initial value of the variable X.

× = Fujunomiya Yi. ．． ．． ．． -■ Upper and lower 4 bytes of X, Y as XHi, YHi, XL
When i, YHi, the lower 4 bytes of the i-th loop are as follows.

i-1 XLi=XL.

10i≧. YLr...'3} At this time, if the carry transmitted from the lower 4 bytes to the higher order is Ci, then the operation result of the upper 4 bytes to be obtained in the i-th loop is expressed by the following equation.

X ratio =
...+;≦;The final calculation result is obtained by Y mountain, 10th room, 3 Ci--...-'51.

In the present invention, by using flip-flops 10 and 11 that transfer data from the lower 4 bytes to the upper 4 bytes, 8-byte operations can be performed without the overhead of continuous addition and subtraction.

In other words, in the arithmetic loop, the carry from the lower order to be transmitted in the i-th loop is transferred to the carry 1 from the previous cycle.
”-Ci-1. That is, j-1 Therefore, at the end of the nth loop, X...=
From X ground to 10; Y mountain 10 guests Ci--...-{71 is obtained, and the difference between the above formula [5} and the {7} formula is that the carry Cn-1 from the bottom of the last round is is just smaller.

So, after n loops, XHn+1=XHn+Cn
-1...'81, a result equal to the result of the upper 4 bytes of the arithmetic loop of formula (2) can be obtained.

In the first calculation cycle (ICYL) in FIG.
In a machine cycle, the adders 6 and 7 for the upper 4 bytes and the lower 4 bytes perform calculations, and the calculation results are set in the x register 4.

In this case, the carry from the lower 4 bytes to the adder 6 of the upper 4 bytes is forced to "0".

At the end of the first operation cycle (ICYL), the carry from the lower 4 bytes to the upper order is set to the latch (FFIO), and in the second operation cycle (20YL), the carry from the lower 4 bytes to the upper
It is added as a carry from the lower 4 bytes to the byte. Further, in the second operation cycle (20YL), the operation result is set in the x register 4, and the carry from the lower 4 bytes to the upper 4 bytes is set in the flip-flops 10 and 11. Thereafter, in the same manner, at the end of the nth calculation loop, the correct value of the following equation is obtained in the lower four bytes of the X register 4. X machine = X mountain ten harms; Yke...
[91 On the other hand, the value of the above formula (7) is obtained in the upper 4 bytes of the X register 4, but this value is the lower 4 bytes in the nth cycle.
It is less by the carry amount from the byte to the upper byte.

Therefore, in the (n+1)th operation cycle, the X register 4
The final result of the upper 4 bytes is obtained by adding the carry of the nth cycle to the upper 4 bytes of .
That is, in the final addition, the Y-side inputs of the adders 6 and 7 of the upper 4 bytes and lower 4 bytes are forced to 0, and the operation of ×+0 is executed. The contents of the flip-flop 11 may be transmitted as a carry to the flip-flop 6. In this way, adders 6, 7
In this case, n calculation loops can be realized by repeating addition n+1 times.

To achieve this, a control means is required to forcibly set the carry from the lower order to "0" in the first cycle, and to forcibly set the Y-side input to "0" in the final cycle, It is sufficient if there is a control means that can input the contents of 11 as a carry from the lower order to the adder 6 of the upper 4 bytes. In addition, to the X or Y side input of adders 6 and 7,
By providing a several-bit left pre-shifter and a 1G Hayabusa correction circuit, a binary number can be converted to a 1-bit Hayabusa number.

In this case, the output of the pre-shifter going from the lower to the upper
This can be easily realized by providing the flip-flops 10 and 11 shown in FIG. 2 and controlling as explained in FIG. 6.
In this way, in a functionally distributed arithmetic unit as shown in Figure 1, if it is difficult to place the adder of G unit 3 in a nearby area due to implementation constraints, the adder of G unit 3 can be While applying the present invention, the adder of F unit 2 is designed to perform carry of a desired data width in one machine cycle.

Note that if multiplication/division and floating point instructions are selected as the operation instructions for the F unit 2, it is expected that the binary addition/subtraction to be executed by the G unit 3 will be approximately 4 bytes. As explained above, according to the present invention, when it is difficult to realize the delay time of an adder with a number of digits suitable for the data width of the information processing device within a predetermined machine cycle, It is possible to realize an adder with the same data width as the device without degrading performance. Note that the present invention provides a functionally distributed arithmetic unit,
This is particularly effective, but is not limited to this, and is generally effective when applied to adders with large propagation delays due to printed patterns.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a functionally distributed arithmetic unit, FIG. 2 is a block diagram of an adder showing an embodiment of the present invention, and FIGS. FIG. 5 is a block diagram of the condition determination section of the comparison instruction in FIG. 2, and FIG. 6 is an explanatory diagram of the continuous addition operation in FIG. 2. 1: arithmetic unit, 2: first arithmetic unit (F unit),
3: Second arithmetic unit (G unit), 4: X register, 5: Y register, 6: Upper 4-byte adder, 7: Lower 4-byte adder, 8, 9: Upper and lower output registers, 10 : Carry transmission flip-flop, 11: Delay flip-flop, 12: Condition judgment section, 13-
16: Inversion circuit, 17-21: AND circuit, 22, 23
:OR circuit. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1. An upper adder that calculates the upper part of the input data length;
a low-order adder that calculates a low-order part; two adders each outputting a calculation result in one cycle; a first flip-flop that holds a carry to a high-order position generated in the low-order adder; a second flip-flop that provides a carry of the flip-flop to the upper adder in the next cycle;
and equality in the upper adder, which operates at the time of the comparison instruction,
It has a case determination means for inputting and determining the presence or absence of a carry, the equality in the lower adder, and the presence or absence of a carry, and when an addition command is issued, inputs the lower order in the first cycle and checks the lower adder. After addition, in the second cycle, the upper part is input and added by the upper adder, and at the time of a comparison instruction, the upper and lower parts are subtracted at the same time, and the condition judgment is performed without propagating the carry from the lower part to the upper part. An arithmetic control method characterized by making decisions using means.