JPS6029409B2 - Trigonometric function calculation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a trigonometric function calculation device for an N-ary computer that calculates trigonometric function values for input angular variables, and particularly to a device that calculates the trigonometric function values by coordinate transformation.

Traditionally, methods for calculating trigonometric function values using electronic desktop calculators include methods that use approximations such as series expansion, and methods that use numerical solutions of ordinary differential equations, but all of these calculation methods are complicated. However, there is a drawback that the calculation time is too long to perform the calculation with sufficient accuracy.

Furthermore, there is a drawback that different normalization is required depending on the angle unit system such as degrees (decimal degrees), radians, gradians, etc. An object of the present invention is to provide a trigonometric function calculation device that eliminates the above-mentioned drawbacks.

According to the present invention, there are many gates that are common to the gate group used in normal four arithmetic calculations, and the hardware is simplified.

Also, the output of the numerical value generator tan-IN-K or 1 bit t
By simply setting an-IN-K to be in the same unit system as the unit system of the variable, calculations in any unit system are possible, which eliminates the need for normalization for each unit system and allows calculations with sufficient accuracy. The calculation time required to perform this can be reduced. Hereinafter, the principle and embodiments of the present invention will be explained with reference to the drawings.

The calculation principle of the present invention is CORDIC (CMrdinate).
Abbreviation for RotationDigtaI Computer: Written by Makoto Ichimatsu, “Numerical Calculations of Elementary Functions”, published by Wang Kyoiku Publishing, 1974, see Chapter 3, Section 4).The following is an example of how to calculate the Gn value. I will explain.

Assume that a point (xk, yk) is given on the complex plane, and m
Adding a linear transformation as shown in the equation, we obtain a new point (x river,, yk+,
)make. Expressing the expression '1} in plural form, xk+, 10lyk+, = (xK+iyk) (10i6K
).・・・． ...■, which can be expressed on polar coordinates as shown in Figure 1.

In other words, the linear transformation of equation {1' is converted to a point (xk,
If we create a new point (xk 10,, yk 10,) in addition to yk〉, the new point's radius Rk+ and declination angle Aw will become steep. 2}--'31. Performing the linear transformation of equation '1) in this way means changing the position of the original point to K as shown in equation '3}.
This corresponds to an extension conversion in which the argument is multiplied by k and the argument is rotated by Qk. Here, the new point corresponds to a point that is perpendicular to the original vector in a direction rotated by the declination. Here, this conversion is sequentially repeated from k=0 to k=n-1 for an appropriate 6k column (x.

, Re)→(xn-yn), we obtain the following relational expression. Here, if circle = 0, that is, = 0 is used as the initial value, n = KXoCOSQ yn = KX from the formula '4}.

sinQ...{5
- can be obtained. By calculating K in this '5-formula, it is possible to directly obtain the cosine (cos) value and sine (Sin) value, but according to the operation based on the original principle, xn and yn as a ratio (ne n
) value can be found.

NenQ Lid: Nobori kiln heat smell Kiki Kaoruki...'6}Other trigonometric function values are obtained by converting based on the support value obtained in the above manner.

The present invention provides an apparatus for calculating the support value of an arbitrarily given angle based on the above principle.

That is, in the present invention, the number of inverse positive and negative values (tan-16x), that is, Qk, of the transformation sequence 6k is counted for a given angle Q, and then constant coordinates, for example (1, 0) are given, and the above transformation is performed. Using column 6k, calculate the coordinate position (Xn, yn) of the transformation point on the given angle by stretching and transforming the number of times taught previously, and calculate the positive value of the given angle Q by calculating yn/xn. It is something that gives you support. In the case of an N-ary computer, 6k=N-k is used as the conversion string.

This is because, in the case of an N-ary computer, if the conversion string 6k is set as described above, the linear conversion of the m-formula can be performed by right shifting and addition/subtraction of K digits. Specifically, in the case of binary, 6k = 2-k, and in the case of IG Hayabusa, 6k = 10-k. In the embodiment of the present invention, which will be described later, assuming a decimal computer, 6k = 10-k is used as the conversion string. adopt. A new variable Y
By introducing k=1 and yk, the {1-formula can be expressed as follows. ×k0·=×k−10−2kYkYk0,=10×(Yk+xk)… Formula {7} is used for calculations in the embodiments of the present invention described later.

Next, examples of the present invention will be described. FIG. 2 shows an embodiment of the hardware of an apparatus for calculating trigonometric functions according to the present invention.

In the figure, the portions containing X and x are gates la and 2a.
, 3a, and is hereinafter referred to as an X register. The portion including Y and y is a shift register that circulates and holds data via gates lb, 2b, and 3b, and is hereinafter referred to as the Y register. The part containing Z and z is gate lc, 2b, 3c
This is a register that circulates and holds data via the Z register, and is hereinafter referred to as the Z register. The portion including W and w is a shift register that circulates and holds data via gates ld, 2d, and 3d, and is hereinafter referred to as a W register. FA is a delayed full adder for 1Q Hayabusa calculation whose addition and subtraction can be controlled by input signal C, and calculates (A-B) and (A+B) for inputs A and B. 4 and 5 are gates that select the A side and B side input signals of the full adder FA, respectively, and 4 has gates 3a, 3b, 3c,
Each output of 33d is input, and 5 has gates 3b, 3c,
3d, each output of the numerical value generator S is input.

The numerical value generator S is capable of generating various numerical data. J is calculated using full adder FA, resulting in carry (
When Ca) or Boro (Bo) occurs or gate 6
This is a flip-flop that is set by the output of the full adder FA via the FA. ROM is a read-only memory that stores instruction codes that control the operation of each gate.
The ADC is an address counter that specifies the address of the read-only memory ROM and controls the program sequence, and the address of the read-only memory ROM is modified by the output of the flip-flop J. ID is an instruction decoder that decodes the instruction code read from the read-on memory ROM and generates micro-instructions to operate each gate, and TE is the decoder ID.
This is a timing generator that generates operation timing for each gate in response to instructions from the gate. FIG. 3 shows the detailed configuration of the x register.

As shown in the figure, the X register is the digit timing ~~Tm
It has a length of m+3 digits corresponding to +2, and the digit corresponding to To is x, T, ~Tm ten, and the digit corresponding to ~xm is x, T.
The digit corresponding to m+2 is called xk. Usually, x stores the decimal point position of numerical data, x stores the numerical data, and Xk is used for various controls. In the following explanation,
The term "x" refers to a tin combination of .times.m to xm, and the term "x register" refers to the entire register. Note that the Y register, Z register, and W register have the same configuration and meaning as the X register. Next, the basic operation shown in FIG. 2 will be explained.

1) Register right shift × Register is normally held by a loop of x → 2a → × → 3a → la →
When S) occurs, T, ~Tm+, time x → 3a → 2a →
By opening the loop of ×, × is shifted to the right.

In this case, since x is one digit, it is shifted one digit to the right.
The same applies to the Y register, Z register, and other timings. 2) When register left shift X left shift command (X is) occurs, X → 3a → 4-F
The loop of A→6-la→x→2a→X is T, ~Tm+,
Open between.

Since the full adder FA has a time delay of one digit, the contents of X are shifted to the left by one digit. However, at this time Full Adder F
No signal is selected as the B-side input of A, so the full adder FA operates as (A10) or (A-0), and the contents of x do not change. Note that the same operation applies to other registers. 3) Addition/subtraction between registers When this instruction occurs, the output of gate 3a or gate 3b is input to the A side input of full adder FA, and the output of another gate 3b or gate 3c is input to the B side input. The output of is input.

At this time, either addition or subtraction is specified by signal C, and the output of the full adder FA is stored in the x register or the Y register through the gate. Also full adder FA
When a carry (Ca) or a borrow (trajectory) occurs as a result of the calculation, a flip-flop J is set and the output of the flip-flop J modifies the address counter ADC. When the next instruction is decoded, the flip-flop J
will be reset. The timing generator TE generates a timing signal to perform an operation and opens the gates mentioned above, but a one-digit delay is added to the gates la to ld to match the delay of the full adder FA. 4) Addition and subtraction of register and numerical data When this instruction is generated, one of the outputs of gates 3a to 3d is input to the A side input of the full adder FA, and the output from the numerical value generator S is input to the B side input. Numerical data is input.

However, the numerical value z is generated only at the first digit of the calculation execution timing, and is set to 0 at other timings. for example,
If X(T,~Tm+,), then the numerical value n will be generated at time T. Addition and subtraction by the full adder FA is performed in the same manner as in case 3) above. 5) Comparison of register contents and numerical values Taking X as an example, the output of gate 3a returns to gate la for normal holding and is input to gate 4, but when this instruction occurs, the execution timing Gate 4 selects the output of gate 3a as the A-side input of the full adder FA, and gate 5 selects the output of the numerical value generator S as the B-side input to perform subtraction.

The result of this calculation is input to flip-flop J via gate 6, but not to gate la. Therefore, flip-flop J is not set when the subtraction result is 0, and is set otherwise, and the contents of the register do not change. Note that the same operation is performed for other registers. 6)
Load numeric data into register When this instruction occurs, gate 4 does not select any signal as the A-side input of the full adder FA, gate 5 selects the output of the numeric generator S as the B-side input, and the full・Adder FA
Instructs addition by .

The output of the full adder FA is the input gate of the register selected by gate 6 (for example, if it is an
A) is input during the execution timing. At this time, the numerical value generator S can generate different data for each digit. The timing of the input gates la to ld of the register is delayed by one dish from the above 3). 7) Data transfer from X register to other registers Taking the data transfer instruction to Y register as an example, the output of ×(T, ~Tm+,) is inputted to the A side input of 3a→4→FA Gate 5 does not select any signal as the B-side input of FA.

The output of the full adder FA is input to gate lb via gate 6. Since the output from the full adder FA is delayed by one digit, gate lb is connected to gate 6 between T2 and Tm+2.
The output of gate 3b is sent to y, and the output of gate 3b is sent to y. 8) Data transfer from other registers to × register Z
Taking the transfer of Zk from the register as an example, Zk(Tm+2
) is input as the B-side input of 3c→5→FA, while the gate 4 does not select any signal as the A-side input of FA.

The output from the full adder FA passes through gate 6 to gate l.
input to a. Since the output from the full adder FA is delayed by one digit, gate la sends the output of gate 6 to x during To, and otherwise sends the output of gate 3a to x.
Next, the calculation operation according to this embodiment will be explained with reference to FIG. 4, which shows an example of a flowchart for causing the hardware shown in FIG. 2 to calculate a bigonometric function according to the present invention. First, in step 1, the hardware operation 6) described above is performed to store numerical data 0 in Xk.

This is because it is necessary to clear Xk since it is used as a counter for the end of calculation. In the next step 2, the hardware operation 6) described above is performed to load 1 digit n-110-K into Y from the numerical value generator S. 1bitan
The value of -110-K is expressed in degrees as an angular unit system.
The numerical value loaded differs depending on whether the standard is ree), radian, or gradian (bait adian).

Table 1 shows tan- for each unit system from k=0 to 4 as an example.
110-K value is shown. Incidentally, gradian is a unit system used in Europe, where 9 egree = 10 cough r.
It is related to adian. Hereinafter, this example will be explained assuming that radians are adopted as the unit system, but if another unit system is used as the standard, the value of 1 dimension n-110-K in the following explanation can be changed to other values. If you replace it with the value of the unit system, the explanation will be exactly the same. Table 1: tan-110-K For example, when the basic unit is radian as in this embodiment, this value is 0.7853 when K=0, and 0.9966 when K=1.

FIG. 5 shows how data is loaded into the Y register when K=0. At this time, it is assumed that the operand (angle variable) has already been loaded into the x register and the decimal point is fixed at the position of Xm. Furthermore, it is assumed that all digits of Z and W are loaded with 0 as data in both registers Z and W, and are cleared. In steps 3 and 4, Y is subtracted from X until a borrow is produced, and the number of loops until just before a borrow is produced is stored in B. Here, the hardware operates by selecting x as the A-side input of the FA and Y as the B-side input and putting the subtraction result in x, and in step 4, selecting Z as the A-side input of the FA, T. from the numerical generator S as a side input. 1 generated at the timing of
are selected and the addition results are stored in B, thereby performing the above-mentioned operations 3) and 4) in both steps. In step 5, subtraction is performed until Bo is generated in step 3, so it is in a state where it has been subtracted one time too much, so to return to the original state, change the A side input of FA to Addition is performed using the Y register and the calculation timing as T, to Tm+.

This is the addition of operation 3) above. In step 6 ×
Performs a left shift. This is to ensure that the data from the numerical value generator S is always loaded from Ym-, and the number of effective digits is not reduced. Therefore, in a simple electronic desktop calculator, step 6 is not necessary if n-110-K is loaded from a numerical value generator. In step 7, Z is shifted to the left. This is to store the number of subtractions in step 3 corresponding to the next value of Xk since the calculation of this value of xk has been completed. In steps 6 and 7, the aforementioned hardware operation 2) is performed for X in the x register and Z in the Z register. In the next step 8, FA
The above-mentioned hardware operation 4) is performed by selecting the X register as the A-side input and the numerical data 1 generated by the numerical value generator S at the timing xk as the B-side input. This operation is to increment the digit counter Xk. In step 9, the content Xk of the digit counter is compared with the numerical data to determine whether calculations have been made for the number of digits. This step is performed by selecting and subtracting m generated at the timing Tm+2 from the x register on the A side input of the FA and N on the B side as described in hardware operation 4). In the steps up to step 9, the process of expressing the contents of × in the '41 formula as a partial sum of the sequence of numbers in Table 1 is completed, and Z is the number of times each numerical value is used.
is stored corresponding to the value of .

This time, we will perform the linear transformation of Equation 11, but here it will be calculated with a new variable YK=1pyyK introduced as shown in the equation. At this point, K=i in Z as the content of Z.
The number of subtractions (i=0 to m) is stored. Also, the remainder from the subtraction remains in X. Here, there is a method to improve the calculation speed by using the remainder of the subtraction of Load the digit with 0 and clear it. In the next step 12, similarly, the hardware operation 6) sets the operation timing to Tm0,
Select , load 1 into ×m, and use this as the initial value. In this way, given the coordinates (1, 0), we used the 6
If we use K and extend the transformation by the number of times taught above, we can obtain the coordinate position of the transformation point on the given angle (xm
yn) is found. In step 13, 1 is subtracted from Z.

If Zo=0, then B. If Bo is not generated, the process moves to step 14. The operation of this part is as described in hardware operation 4). Step 1
4, a value obtained by adding the contents of X and Y by one tone is stored in the Y register. In step 15, the content of Y shifted to the right 2K times is subtracted from x. Here K is the content of Xk. This K-digit right shift and subtraction can be realized, for example, by a combination of instructions as shown in FIG. In FIG. 6, in step 1, the contents of xk are transferred to Zk.

This is to preserve the contents of Xk since xx will be destroyed by the following calculation. This operation is as described in hardware operation 7), and the Z register is used instead of the Y register.
This can be realized by using a register and setting the operation timing to Tm+2. Subsequently, in step 2, the contents of Y are transferred to W. This can also be realized by setting the timing of the operation described in hardware operation 7) to T, .about.T. In step 3, 1 is subtracted from Xk, so if Xk=1, Bo is generated, and if Bo is generated, the process goes to step 6, and if B is not generated, the process goes to step 4. In steps 4 and 5, W is shifted to the right. Therefore, by going through this loop until Mr. is generated, the content of Y becomes Xk
The content of ×k is shifted to the right by 2 times, and the content of ×k is K by 10-
Sphere Y is obtained in W register. When & is generated in step 3, W is subtracted from X in step 6, and the difference is stored in the x register. As mentioned above, step 2
~6 gives x-10-shoes Y at x. Step 7
This is for restoring to Xk the contents of Xk that were destroyed in step 3 of transferring to ZK as described in hardware operation 8). Returning to the explanation of FIG. 4 again.

Steps 13-15 are multiplication routines for specific values of K. In step 13, a horse is generated and the process moves to step 16, where Z is set to the number of subtractions for the next K value.
Shift right one place. In the next step 17, Y is shifted one digit to the right for digit alignment. Subsequently, step 18 of subtracting 1 from Xk in order to decrement the value of K is a step for detecting the end of this operation, and when the value of Xk is reduced by 1 to produce Bo, this operation ends and X The right side of xn in the {5-formula is in the register, and the Y register is [
5} The right side of yn in the equation can be found. As mentioned above, in calculations using this method, the positive value is given as the ratio of the X register and the Y register, so in order to obtain the positive value, the contents of the Y register are must be divided by the contents of .

This method is a simple division and is carried out as shown in FIG. In step 1 of FIG. 7, 0 is loaded into Xk to clear xk.

In step 2, data is transferred from X to W. In step 3, the output of the Y register is selected on the A side of the FA, and the output of the W register is selected on the B side, and division is performed at the timing of T, to T sail. If B occurs in this step, the process proceeds to step 5; if Bo does not occur, the process proceeds to step 4. In step 4, 1 is added to B in order to store the number of divisions for a specific value of K. If & is generated in step 3, it means that one too many subtractions have been made, so Y+W is added to restore the original state. In the next step 6, Y is shifted to the left so that the next value of K can be divided again. In step 7, Z is shifted to the left so that the number of divisions for the next K value can be stored. In step 8, 1 is added to Xk to increment the value of K. In the next step 9, the step xk for determining the end of the calculation is compared with the output m of the numerical value generator S, and if K=m, the calculation ends. Also K
When ≠m, return to step 3 again and repeat the operations described above. In the end, the content of Z becomes the desired value. In the above description, a register is used as a storage device, but it is of course possible to use a RAM (random access memory) as this storage device.

In addition, if a part of the instructions read from the ROM is configured so that it is input into a register as numerical data when a specific instruction is read, the numerical value generator S becomes unnecessary, and the numerical value generator S can be generated in the ROM. It is possible to substitute

[Brief explanation of the drawing]

Figure 1 shows the linear transformation, which is the calculation principle of the present invention, as a point on polar coordinates, where (xk, yk) is the point before the linear transformation is applied, and the linear transformation is applied to this point ( xk…yk+,
). FIG. 2 is a block diagram showing an embodiment of the present invention, in which x,
y, z, X, Y, Z Hashijista; la, 2a, 3a, l
b, 2b, 3b. lc, 2c, 3c, ld, 2d, 3d
, 4, 5, and 6 are gates; FA is a delayed full adder; ADC is an address counter; ■ is an instruction decoder; J is a flip-flop; ROM is a read
Only memory; S is a number generator; TE is a timing generator. FIG. 3 is a diagram showing the detailed configuration of the X register in FIG. 2. Figure 4 shows x according to the principles of the invention.
It is a figure which showed the flowchart just before calculating|requiring a support value as a ratio of a register and a Y register. FIG. 5 is a diagram showing the state in which tan-110-K is loaded into the Y register in units of radians. FIG. 6 is a diagram showing an example of a flowchart of K-digit right shift and subtraction used in FIG. 4. FIG. 7 is a diagram showing an example of a flowchart following the flowchart of FIG. 4, in which the support value is obtained in the Z register as the ratio of the X register and the Y register.
Figure 1 Figure 2 Figure 3 Figure 5 World Map Figure 6 Garden Figure 7

Claims (1)

[Claims] 1. In a trigonometric function calculation device in an N-ary computer that calculates trigonometric function values for input angular variables, a first storage means for storing the input angular variables, and a first storage means for storing the input angular variables, and a first storage means for storing the input angular variables, Arc tangent value tan^-^
1N^-^K or 10^Ktan^-^1N^-^K
means for successively generating from K=0 to a positive integer m; means for repeatedly subtracting the arctangent value for a fixed K from the first storage means until immediately before a borrow occurs; a second storage means for storing data corresponding to;
a third storage means, a fourth storage means, a means for right-shifting the contents of the fourth storage means by a number of digits twice the fixed value of K, and contents of the first storage means. means for adding the contents of the fourth storage means to the contents of the third storage means; means for subtracting the contents of the fourth storage means from the contents of the first storage means; and means for transferring the stored contents from one of the storage means to another storage means,
The above-mentioned arctangent values sequentially generated corresponding to each value up to m are subtracted from the above-mentioned first storage means corresponding to each value of K until a borrow occurs, and the number of subtractions until immediately before a borrow occurs is calculated. After storing it in the second storage means corresponding to K, and repeating the above operation from 0 to m with the value of K,
The content of the first storage means is set to 0, the first storage means is set to 1, and the third storage means is set for the number of subtractions corresponding to K.
The value obtained by adding the contents of the first storage means to the contents of the storage means is multiplied by 10, and the contents of the third storage means are transferred to the fourth storage means, and the contents of the fourth storage means are Shift to the right by twice the number of digits of the value of K, and then
The contents of the first storage means after repeating the operation of subtracting the contents of the fourth storage means from the contents of the storage means of , and repeating this operation until the value of K becomes from 0 to m, and the contents of the third storage means A trigonometric function calculation device characterized in that the tangent value of the angle variable is obtained as a ratio of the contents of the storage means.