JPS6029914B2 - electronic clock - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece in which the oscillation frequency of an oscillator temporarily fluctuates due to external impact.

An object of the present invention is to improve time accuracy by using a frequency divider to reduce the influence of temporary fluctuations in the oscillator frequency caused by external shocks. Another object of the present invention is to simplify the structure of the oscillator by reducing the influence of temporary oscillation frequency fluctuations with a frequency divider;
The object of the present invention is to provide an oscillator that is easier to manufacture and cheaper.

Conventionally, most of the oscillators of electronic watches are based on sound or mechanical vibrations such as crystal oscillators, and the oscillator frequency is easily affected by external influences, and the frequency temporarily decreases when an impact occurs.

Although both the rate of decline and the time taken at this time are not so large, repeated impacts cause an integration error in the time. Particularly for watches that are carried around, such as wristwatches, there are many shocks and the impact varies depending on the conditions, which is a major cause of deterioration of time accuracy.

Furthermore, many improvements have been made to oscillators to make them less susceptible to such external shocks, making the shape, processing, and mounting and supporting methods of the oscillators complicated, making them expensive and unsuitable for mass production. The present invention eliminates such drawbacks, and FIG. 1 shows a block diagram of an embodiment according to the present invention. Furthermore, FIG. 2 shows how the oscillation frequency changes when an impact is applied. The fluctuation rate and fluctuation time of the frequency are generally about 0.0001% and 0.2 seconds, respectively, and if a shock is applied at a rate of 1 time, the cumulative error for 1 month is about 0.0001%. Becomes mother sand. In Figure 1, 1 is an oscillator, 2 is a delay mechanism, 3, 4, and 6 are frequency dividers,
5 is a logical product mechanism, and 7 is a display mechanism. Frequency divider 3 and 4
are frequency dividers having the same frequency and the same frequency, and the delay machine 2 has a delay time corresponding to one period of the frequency dividers 5 and 4. Therefore, frequency dividers 3 and 4 operate with a time difference equivalent to one frequency divider, and even if there is a temporary fluctuation in the oscillation frequency of oscillator 1, in most cases, one frequency divider will operate normally. The oscillator frequency can be divided and transmitted to the next stage frequency divider 6. A specific example using an electronic circuit will be explained in detail with reference to FIGS. 3 and 4.

In Figure 3, 1 is an oscillation circuit, 2 is a frequency divider circuit A, 3 is a delay circuit, 4 is a frequency divider circuit B, 5 is a frequency divider circuit C, and 6 is an AND circuit.
7 is a reset timing circuit, 8 is a frequency dividing circuit D, and FIG. 4 shows a timing diagram of each part. As shown in FIG. 4, when the oscillation frequency fluctuates at the time of period 2, the output of the frequency divider circuit C5 changes to the oscillation frequency at period 2, as shown by the broken line in FIG. It is expected to be extended in response to the decline in

However, since the frequency dividing circuit B4 operates with a delay of one cycle due to the delay circuit 3, the output is completely normal in the second cycle. Therefore, the output of the AND circuit 6 becomes as shown in FIG. 4, and at the rising edge of this waveform, a reset pulse is output, and both the frequency dividing circuit B4 and the frequency dividing circuit C5 are reset. In the next cycle 3, the frequency divider circuit C5 has already returned to the normal output, and the frequency divider circuit B4 is about to be extended as shown by the broken line.

However, as in the case of period 2, the input pulse to the frequency dividing circuit 08 becomes completely normal. In this way, if the fluctuation of the oscillation frequency continues within one cycle of the frequency divider circuit,
Does not affect time accuracy at all.

If the frequency fluctuation extends over two periods, an error will appear, but since only the period with the least fluctuation of the two periods will be an error, it will be small quantitatively, compared to the case of no correction at all.
The time delay can be reduced to within 1/5. As described above, according to the present invention, time errors due to temporary fluctuations in oscillation frequency caused by external shocks can be reduced, and time accuracy can be improved.

Furthermore, by correcting errors due to temporary fluctuations using a frequency divider, the structure and manufacturing method of the oscillator can be simplified, and an inexpensive oscillator can be provided.

[Brief explanation of drawings]

FIG. 1 shows a block diagram of an electronic timepiece according to the invention. Figure 2 shows how the frequency changes when an impact is applied. FIG. 3 shows a specific example of a frequency divider using an electronic circuit. FIG. 4 shows a timing diagram of each part in the electronic circuit of FIG. Traditional 1 drawing Tsutomu 2 drawing Blue drawing Tsutomu 4 drawing

Claims (1)

[Claims] 1 oscillator, delay circuit, first frequency divider, second frequency divider,
It consists of an AND circuit, a third frequency divider, and a display mechanism, the output of the oscillator is input to the delay circuit and the second frequency divider, respectively, and the output of the delay circuit is input to the AND circuit. The output of the first frequency divider and the output of the second frequency divider are respectively input, and the display mechanism displays the output of the third frequency divider that divides the output of the AND circuit. An electronic clock characterized by: