JPS6030026B2 - Skew correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is applicable to devices in which independent information signals from multiple devices or circuits need to be synchronized to a single reference clock signal.

In particular, an information storage device that performs parallel writing and reading and transfers information and its control device are usually required. Information that is normally transferred in parallel is not received at the same time even if it is transmitted at the same timing on the transmitting side due to variations in circuits, transmission systems, elements, etc., so there is a risk that the receiving side may erroneously decode the information.

In order to prevent such problems, a disk buffer circuit is required to correct temporal variations in input information.
Conventionally, various methods have been considered for disk buffer circuits. In other words, there are analog detection and correction methods, digital methods that generate a reference clock with a cycle shorter than the bit length of the input signal, perform scanning using this clock, detect the amount of skew, and correct it, and special methods. A method that does not generate a standard reference clock but detects and corrects the skew amount only for each specific bit of input information, and a method that digitally waits for the latest input information of each input signal system and performs correction. etc.

However, both of these methods require a large amount of material, and analog methods have large variations in the range that can be corrected, and scanning methods require the generation of a special reference clock, and control requires waiting for the last input information. This causes problems such as the processing time in this circuit becoming longer. To ameliorate these problems, the present invention provides a means for processing based on the information that comes first. The following is a brief explanation of the circuits used. FIG. 4 shows a conventional deskew buffer circuit.

This method shifts input signals to registers (storage devices) one after another, checks whether information is input in the register to be shifted, and then inputs the information.
If it is stored, the bit stops at that storage device, and if the register to be shifted does not contain information, it continues on to the next register. If this is done, information will always be input into the register on the most output side of each signal system. However, if information is input to the output stage of a certain input system register due to skew, but no information is input to the output stage of another input information system register, wait for that information to arrive. If information is input into the final register of the input information system, it is output at the same timing. Once the information in the last register is output, there is no more information in the storage section, so the next information is transferred from the previous register. In FIG. 4, information on the input A side includes information Ao to A4 inputted to registers (storage devices) from ao to a7.
Since information Ao has already been moved to the final register part of ao, it will wait until information Bo is shifted widely, and when information Bo is input to the input, Ao and Bo will be transferred at the same timing.
output the information. Information A, . To the information, Mr. can shift the information because there is no information entered in the register to which it should be shifted. In this way, the outputs can be output at the same timing.

However, in this method, when shifting information, it is necessary to confirm whether the information is input in the register to be shifted, so a confirmation circuit is required, and the operation time is long, so it is not possible to make it ultra-speedy. It is no longer applicable to the transfer of information that The purpose of this invention is to use a compact circuit that does not require a large number of parts, and to operate entirely under digital control. It is an object of the present invention to provide a skew correction circuit which is capable of operating even when the amount of skew changes both in delay and advance, and in which the skew amount to be corrected is symmetrical in both delay and advance.

Another object of the present invention is to provide a circuit configuration that can easily detect overskew. The feature of the present invention is that it is a register file type disk buffer circuit, which uses the reference clock of the earliest input signal system among multiple input signals input independently. This is an attempt to digitally correct the skew based on the central value up to a range of variation that is symmetrical to the center value.

Since the maximum amount of skew itself can be calculated in advance, the input signal is configured so that it can be stored in a register (in a storage device) for a period of time equal to that amount of time. The stored input signals from each series are simultaneously read out after a time period corresponding to the amount of skew that may occur from the input signals.

FIG. 1 shows the circuit configuration of the present invention, and FIG. 2 shows its operating signals.

Here, for the sake of explanation, the input information is assumed to be two series, and the information from each circuit is parallel information A synchronized with the reference clock.
-0, B-0 to A-x, B-x. Further, the number of cells in the storage device is set from 0 to 7, and the number of bits per cell is x, which is the same as the number of parallel input information. The clock A outputs A3A from the binary coded signals A and A input to the counter circuit 1 and inputs it to the data write circuit 3.

Here, the input signal is converted into a signal for selecting a designated cell of the storage device 5, and the input information data A-0 to A-x are stored in the same cell using the write designation timing signal BA. The storage device 5 is writable and readable, and can be read and written at the same time. In the memory device 5, input information is stored one after another from cells 0 to 7 according to the write designation timing signal BA generated based on the clock A, and when cell 7 is stored, the input information is stored in cell 0 again.
Go back and memorize the next input information. When expressed as timing signals, they become signals DAo to DA7. Similarly, the input signal from the B-side circuit and its reference clock perform the same operation, and the information in the storage device 6 changes from signal DB to DB. Here, it is assumed that the input from the B side is delayed with respect to the input information from the A side. Counter circuit 1
, 2 are input to the clock detection circuit 7. The clock detection circuit 7 detects the side of the input information from the A and B circuits that is stored in the storage device first and outputs the signal TD, and the clock switching circuit 8 outputs the clock from the side that was input first. Give instructions. A signal from the clock detection circuit 7 causes the clock synchronization delay circuit 11 to operate so that a specific period of time can elapse from the time it starts operating. This specific time is determined depending on the range in which overskew is to be detected. In addition, there are times when the skew amount fluctuates and there is no margin when inputting to the storage device but outputting it, so the clock detection circuit 7 detects a situation where such a situation may occur and controls this delay time. let Here, the delay is set to 4 clock bits, and the signal DL is output. The counter circuit 12 starts its operation by the DL signal whose start point is controlled, and then receives the signals C,
A outputs signals C and C, and data reading circuits 13 and 14
The data selector circuits 9 and 101 convert the signals C, A to C, C from the designated counter circuit 12 into such a manner that the information stored in the storage device can be output. Information from the storage devices 5 and 6 is presented one after another. The discussion at this time is performed at the same timing for both storage devices 5 and 6. The output clock generation circuit 17 transfers the information read from the storage devices 5 and 6 to the register circuit 1.
It generates a trigger pulse RC to be taken into the register circuits 5 and 16, and outputs a clock signal C synchronized with the output signals data AC and data BC from the register circuits 15 and 16. The signal DC in FIG. 2 is the information read from the storage devices 5 and 6 from the signal TC and DL', and the information 0 to x from the A side and the information 0 to x from the B side are read in parallel. Representative bits are shown, and data AC and data BC signals are shown as representative parallel information bits. FIG. 3 shows information DAo to DAx, DBo stored in the storage devices 5 and 6.
This is a diagram showing the timing of reading out DBz, and when the signal DL output from the clock synchronization delay circuit 11 is fixed (here, 4 clock bit length delay: T), information is read out at each point X. When the signal DL is controlled, for example, when the stored information is displayed at the timing of the best point, the signal DL changes to, tx, ty, and X.
It is read out at the timing of point '. When the signal DL is controlled, a plurality of stages of resistor circuits 15 and 16 may be required. According to the present invention, the extraction point from the storage device can be controlled depending on the state of skew fluctuation.

(The overskew amount detection range can be easily changed.
) A signal for detecting overskew can be sent from this circuit to another device. There is no special signal generated within this circuit (no need for an oscillator, etc.).

) Can be controlled using only input signals. It can cope with the ultra-high speed of input information.

[Brief explanation of the drawing]

Fig. 1 is a circuit configuration diagram of the present invention, Fig. 2 is a time chart of each part in Fig. 1, Fig. 3 is a diagram for further explaining the state of the operation signal of a part of Fig. A schematic configuration diagram of an example is shown. 1, 2... Counter circuit, 3, 4... Data writing circuit, 5, 6... Memory device, 7... Clock detection circuit, 8... clock switching circuit, 9,
10...Data selector circuit, 11...
・Clock synchronization delay circuit, 12... Counter circuit, 13, 14... Data detection circuit, 1
5, 16...Register circuit, 17...Output clock generation circuit. 3 diagrams, 4 diagrams, O-diagrams, O-Z diagrams

Claims (1)

[Claims] 1 In a skew correction circuit that outputs information from multiple independent circuits in synchronization with a single reference clock, it is possible to perform write and read operations, and it is possible to write to a memory section and read from the same memory section at the same time. A storage device, a circuit that independently stores input information from each independent circuit in the storage device using an input information clock, and an input of information that arrives earliest among the independent input information clocks. It is characterized by comprising a circuit that simultaneously reads the information at the corresponding position in each storage device according to the order of the input information based on the clock after a specific time has elapsed from the information clock. skew correction circuit.