JPS6030027B2 - Skew correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a skew correction circuit used to correct phase differences between channels when reproducing data digitally recorded on a magnetic tape device or the like.

When reproducing self-clockable data recorded on a magnetic tape or the like, it is necessary to correct the skew (data phase difference between tracks) after reproducing the data for each channel.

FIG. 1 shows a conventional skew correction circuit. Although the parts surrounded by dotted lines are necessary for the number of channels, only one channel is shown here. 1 is a 4-stage ring counter with 1→
Count in the order of 2 → 3 → 4 → 1 → 2.

2 is a 4-stage deskew buffer, and 3 is a data selection circuit.

4 is a comparison circuit, and 5 is a clock generation circuit. 6 is a ring counter that counts in the order of 1 → 2 → 2 → 4 → 1 → 2.

music played for each channel. The counter to which the clock is input is incremented by 1, and the data is set in the disk buffer 2. Suppose that ring counter 1 is (n
-1), when the clock is input, the ring counter 1 changes to n. At this time, the data contents are set in the nth stage register of the descuba buffer. The ring counter 6 changes by n' from (n-1) when data is prepared in the nth stage of the deskew buffers of all channels. At this time, the data selection circuit 3 selects the nth stage among the outputs of the deskew buffer 2. That is, after the data of the channel with the most delayed phase is taken into the deskew buffer 2, the ring counter 6 adjusts the phase of the data and takes it out. Comparison circuit 4 triggers clock generator 5 when data is prepared for all channels, and generates a clock to be input to ring counter 6. That is, when the ring counter 6 indicates n, the ring counters 1 of all channels are (n + 1),
If either (n+2) or (n+3) is indicated, a trigger signal is generated. Comparison circuit 4 detects that a skew exceeding the capacity of the deskew buffer has occurred and generates an overflow signal. That is, ring counter 6
indicates n, and if even one of the ring counters of all channels indicates (n-1), an overflow signal is generated. As an example, when the ring counter 6 indicates 2, when data is prepared in the third stage of the channel with the most phase delay, the ring counters 1 of all channels indicate 3, 4, or 1, Trigger the clock generation circuit. At this time, ring counter 1 is 1.
If it still shows 1, an overflow signal is generated. As is clear from the above example, even though the deskew buffer is configured with four stages, if a skew of three or more stages occurs, an overflow occurs. That is, in order to allow n stages of skew, it is necessary to configure a deskew buffer with (n+2) stages. In this way, in the conventional circuit, n
In order to tolerate the skew of the stages, it is necessary to construct a deskew buffer of (n12) stages, which makes the circuit complicated.

If a magnetic tape device is to allow two stages of skew, nine channels of four stages of deskew buffers are required.
The purpose of the present invention is to reproduce data from a magnetic tape.
An object of the present invention is to provide a skew correction circuit with a simple circuit configuration.

The feature of the present invention is that it is set when data is taken into the deskew buffer, and when the data is taken out, the IJ
By preparing a flag to be set and using this flag to detect overflow and create timing to match the phase of data in all channels, the number of deskew buffer stages can be reduced.

The configuration of the present invention will be explained with reference to FIG.

Reference numeral 11 denotes a counter that specifies the descuba buffer 12 from which data is to be taken.

14 is a flag that is set when data is taken into the descuba buffer 12 and reset when data is taken out; 15 is a comparison circuit that compares the flag states within the channels to detect overflow; 16 is a comparison circuit between all channels. A comparison circuit compares the flag states and determines the timing to take out data, and 13 is a data selection circuit that takes out data from the deskew huffer.

The present invention will be explained in detail with reference to the embodiment shown in FIG.

Although the number of channels within the dotted line is the same as the number of channels, only one channel is shown here.

11 is a binary counter, 12 is a two-stage deskew buffer, 13 is a data selection circuit, and 14 is a flag indicating the state of the deskew buffer consisting of two-stage flip-flops.

17, 18, and 19 are AND gates, 20, 21 are delay lines, and 22, 23 are OR gates.

When the clock reproduced for each channel is input to the binary counter 1, its output alternately repeats "1" and "0", and the data contents are loaded into the deskew buffer 12.
When the output of the binary counter 11 changes from "0" to "1", data is taken into the flip-flop F, which is the first stage of the descuffer.

Further, the flip-flop F3 in the first stage of the flag 14 is set to indicate that the first stage' of the deskew buffer 12 and data are prepared. The output of binary counter 1 is “1”
” to “0”, the descuba buffer 12-2
The data is taken into the flip-flop F2 at the second stage, and the flip-flop F4 at the second stage of the flag 14 is set to indicate that data is prepared in the second stage of the deskew buffer 12.

When data is prepared in the first stage of the deskew buffer 12 of all channels, the first stage flip-flop F3 of the flag 14 of all channels is set, and the output of the AND gate 18 becomes "1". After a certain time delay due to two delay lines, this signal is applied to the reset input of the first stage flip-flop F3 of the flag 14 of all channels, and resets the first stage flip-flop F3 of the flag 14. The output of the AND gate 18 is also applied to the data selection circuit 13, which selects the first stage of the deskew buffer 12 and outputs it. The output of delay line 20 is added to the input of OR gate 22 to provide a clock output. When data is taken into the second stage of the deskew buffer of the channel with the most delayed data phase, the second stage flip-flop F4 of the flag 14 is set, the output of the AND gate 19 becomes "1", and the data The selection circuit 13 selects the second stage of the descuba buffer 12.

The output of the AND gate 19 is delayed by the Taylor line 21, and then resets the second-stage flip-flop F4 of the flags 14 of all channels and is added to the input of the OR gate 22, thereby becoming a clock output. Even though data is being captured in both the first and second stages of the deskew buffer in the channel with the most advanced data phase,
If no data is taken into the debuffer in the channel with the most delayed data phase, the first and second flip-flops of the flag 14 of the channel with the most advanced data phase are set.

At this time, when the clock is input, data is taken into the disk buffer, but the previous data is lost. Further, the output of the AND gate 17 becomes "1", and therefore the overflow signal output from the OR gate 23 also becomes "1". That is, when three or more stages of skew occur, an overflow signal is generated. As is clear from the above, in the present invention, in order to tolerate n stages of skew, it is sufficient to configure n stages of deskew buffers, thereby simplifying the circuit.

[Brief explanation of drawings]

Figure 1 is a block diagram showing a conventional deskew buffer.
FIG. 2 is a block diagram showing the configuration of the present invention, and FIG. 3 is a block diagram showing an embodiment of the present invention. 11... force unta, 12... death battle, 13
...Data selection circuit, 14...Flag, 15...Comparison circuit, 16...Comparison circuit. Oh figure 2 figure 3 figure

Claims (1)

[Claims] 1 A counter that specifies the deskew buffer and the deskew buffer from which data is taken, a flag that is set when data is taken into the deskew buffer and reset when data is taken out, and a flag in the channel. It consists of a comparison circuit that compares the states and detects overflow, a comparison circuit that compares the flag states between all channels and determines the timing to take out data, and a data selection circuit that takes out data from the deskew buffer. A skew correction circuit characterized by matching data timing between channels.