JPS6030108B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (11) Technical Field of the Invention The present invention relates to a semiconductor memory device equipped with a PNPN memory cell, and particularly relates to the structure of a PNPN memory cell.

■ Background of the Invention In recent years, in semiconductor memory devices equipped with bipolar memory cells, the switching speed of word line switching and bit line switching during writing/reading, and the reduction in the area required for memory cells have improved dramatically. However, the demand remains high.

[3- Conventional technology and problems/Dipolar memory cells consist of a PNP transistor for load and a multi-chip transistor N that constitutes a flip-flop.
However, since this memory cell was conventionally formed with two diffusion layers, the load PNP transistor had to be constructed with a lateral transistor.

In general, outside of the lateral transistor, the current amplification factor hFE is small, it is difficult to manufacture a transistor so that hFE has a desired value, and the region between the P-type emitter region and the N-type diffusion layer directly below it is used for transistors. Although this region is not necessary for operation, there are problems such as charge being easily accumulated in this region, which makes it undesirable as a memory cell transistor. In other words, the switching speed of a memory cell largely depends on the characteristics of the load PNP transistor, but if hFE is small, the switching speed will be slow, and if hF8 has large manufacturing variations, this will also affect the switching speed. In addition, the accumulation of unnecessary charges in the region immediately below the emitter also adversely affects the switching speed. Furthermore, since the conventional semiconductor memory device has a two-layer structure as described above, all wiring layers are formed on the surface of the semiconductor memory device. The lower limit of the area required for a memory cell is limited by the number of wirings on the surface, and by forming all wiring layers on the surface of a semiconductor memory device as in the past, the area required for a memory cell is large. There were also problems. The problems in the above-mentioned prior art will be explained in more detail with reference to the drawings.

Figure 1 is an equivalent circuit diagram of a conventional memory cell, and Figure 2 is an equivalent circuit diagram of a conventional memory cell.
FIG. 3 is a cross-sectional view showing the physical structure of the memory cell shown in the figure. 1st
In the figure and FIG. 2, the memory cell MC includes a pair of load PNP transistors Q, , Q,' and a pair of multi-emitter NPN transistors Q2, Q3, Q2', Q3' forming a flip-flop. W+, W
- and bit lines BL, BL. As is clear from Figure 2, Multi-Emitsuta NPN
The transistors Q2, Q and Q2', Q3' are formed of vertical transistors, but the load PNP transistors Q, , Q,' are horizontal transistors. Therefore, the widths of the N-type booth regions R and R' of the transistors Q, , Q,' must be formed extremely narrow. The regions R and R are transistors Q,,Q,
' is formed between the P-type diffusion region which becomes the collector and emitter, but it is difficult to control the lateral diffusion and it is difficult to obtain a desired value for the base width. Therefore,
Load transistors Q,,Q. The current amplification factor hFE of ' is not only small, but also involves manufacturing variations. Also,
PN junction region J,, J2 between the P-type region which becomes the emitter region of the transistor Q,,Q,' and the N-type layer immediately below it.
is a region unnecessary for operation as a load transistor; however, this region J. , J2 have a lateral direction in which charges are accumulated. As mentioned above, the switching speed of the memory cell greatly depends on the characteristics of the load transistor, so as mentioned above, hFE is small, there is no manufacturing variation, and unnecessary charges are not accumulated under the emitter region. This causes a delay in the switching speed of memory cells. Also,
As shown in FIG. 2, the wiring, especially the bit lines BL, BL
, and word lines W-, W- are all formed on the surface of the device.

As mentioned above, since the area of the cell is limited by the number of wiring lines, it is preferable to form these wiring lines using a buried layer. (4) Purpose of the Invention The purpose of the present invention is to solve the problems in the conventional form described above.
In a PNPN memory cell, the switching speed is improved based on the concept of configuring the PNP load transistor with a vertical transistor and configuring the memory cell with a three-layer structure to form the word line or bit line in a buried layer. At the same time, the aim is to reduce the required area.

{5) Structure of the Invention The semiconductor memory device of the present invention includes memory cells arranged at each intersection of a plurality of word lines and a plurality of bit lines, each of which has a PNP transistor for load and a PNP transistor for load. , a semiconductor memory device comprising an NPN transistor constituting a flip-flop, characterized in that the load PNP transistor is composed of a vertical transistor, and the word line or the bit line is formed of a buried layer. do.

■ Embodiments of the invention Examples of the invention will be described below based on the drawings.

FIG. 3 is an equivalent circuit diagram showing a memory cell according to an embodiment of the present invention.

In FIG. 3, memory cell MC includes a pair of PNP transistors Q, for load. , Q, o' and a pair of multi-emitter NPN transistors Q forming a flip-flop.
2. , Q, Q' and Qo' are connected between word lines W1, W- and bit lines BL, BL. Among the multi-mittance NPN transistors, the transistor Q2o indicated by a dotted line is called a hold transistor and is used to hold data. Hold transistor Q2
Collector C of o is structurally an emitter, but operationally operates as a collector. Another transistor Q3 is indicated by a dotted line. is called a select transistor, whose emitter Es is connected to the bit line BL, and is a transistor that is forcibly turned on when the bit line BL becomes a low potential at the time of selection. Transistor Q2. The collector (operatingly, it becomes the emitter) EH is the negative side word line W-
It is connected to the. In this embodiment, the load word line W- is shown by a dotted line because it is formed of a buried layer as described later. Multi-emitter transistor Q2o'
, Q's configuration is Q2o,Q. It is similar to FIG. 4 is a cross-sectional view showing the physical structure of the memory cell of FIG. 3.
In FIG. 4, an N-type buried layer 2 which becomes a word line W- is formed on a P-type semiconductor substrate 1 according to the present invention.
On the N+ type buried layer 8, NPN transistors Q2o, Q
o base region and PNP transistor Q,. A P-type region 3 is formed as a collector region. The N-type diffusion layer 4 formed on the surface of the P-type region 3 is the emitter region of the select transistor Qo, and its emitter electrode Es
is connected to the bit line BL'. In addition, P-type region 3
N-type diffusion layer 5 formed on the surface of select transistor Q and hold transistor Q2. The electrode C is connected to the electrode B' of the common base region of the Marchemitsuta transistors Q' and Qo' formed at symmetrical positions across the isolation region 6. There is. P-type diffusion layer 7 formed on the surface of N-type diffusion region 5 is an emitter region of load PNP transistors Q, o, and is connected to word line W+. Symmetrically with respect to isolation region 6, transistors Q,o, Q2o, Q3. and transistors Q, o', Q2o', and Qo' are formed. Reference numeral 8 indicates an isolation region from peripheral transistors such as a discharge circuit, and reference numeral 9 indicates an isolation region in the column direction of the memory cells MC.

The isolation regions 6, 9 are obtained, for example, by oxidation of polycicoline. The separation region 9 in the column direction is separated from the device surface by the P-type substrate 6.
The word line W- is electrically isolated from memory cells in adjacent columns. As is clear from FIG. 4, the load transistors Q, o, Q,.

''It is configured as a vertical transistor. Therefore, the current width ratio hFE of the load transistors Q, o, Q, o'
are conventional load transistors Q,,Q,' (Figs. 1 and 2).
It is large compared to the figure). Further, in the case of a vertical transistor, there is less variation in the manufacture of hFE than in a lateral transistor. Furthermore, by making the load transistor vertical, the amount of unnecessary charge accumulated at each node of the load transistor is reduced, unlike in the conventional case. Therefore, according to this embodiment, the switching speed of the memory cell is increased. Furthermore, by forming the word line W- as a buried layer, the number of wiring lines per memory cell is reduced by two, thereby making it possible to reduce the stripes in the area required for the memory cell.

The structure shown in FIG. 4 has the following problems.

That is, transistor Q3. is the emitter region of N
A transistor Qv is simulated by the P-type region 4, the P-type region 3 immediately below it, and the N-type buried layer 2 immediately below it. In the circuit of FIG. 3, this refined transistor Qv is a transistor whose emitter, base, and collector are the emitter Es of the select transistor Qo, the common base B, and the operational emitter EH of the hold transistor Q2o, respectively. Due to the presence of the pseudo transistor Qv, current may flow through the pseudo transistor Qv even though the memory cell MC is in a non-selected state, resulting in a so-called double selection state. The same thing can of course be said about the transistors Q' and Qo'.
A device proposed to solve this problem is shown in FIG. FIG. 5 is a sectional view showing the physical structure of a semiconductor memory device according to a second embodiment of the present invention.

The difference between FIG. 6 and FIG. 4 is that the P-type regions 3 and 3' immediately below the N-type diffusion regions 4 and 4' (the base of the multi-emitter transistor) are the emitter regions of the select transistor Q side The only difference is that highly impurity-concentrated round regions 10 and 10' are formed in the regions 1 and 2, and the rest of the structure is the same as in FIG. 4 and is designated by the same reference numerals. By providing the P+ type region 10,
The current amplification factor hFE of the pseudo transistor Qv becomes small, and the above-mentioned double selection problem is solved.

Of course, the P-shaped region 10' also has the same effect. FIG. 6 is a principal circuit diagram showing a semiconductor memory device according to the present invention constructed using the memory cells shown in FIG. 4 or FIG. 5.

Since the circuit configuration of a semiconductor memory device itself is well known, only a brief explanation will be provided. In FIG. 6, each memory cell MC, . , . . . , MCnn are arranged at each intersection of the plurality of word lines W10, W- and the plurality of bit lines BL, BL. DiS is a holding current source that supplies holding current to unselected and half-selected cells. BCL is a bit line clamp circuit that fixes the potential of unselected bit lines to a high potential clamp level. B.C.D.
is a bit line drive circuit, which is a circuit that flows a write current and a read current to a selected bit line. DIS,BDC
and BCL are well known matters. The negative word line is shown as a dotted line because it is formed of a buried layer. In addition, in the explanation of the above embodiment, the negative side word line W- was formed with an N+ type buried layer, but instead of this, it is also possible according to the present invention to form the bit line BL with an N type buried layer. It is clear to those skilled in the art that the following is true: o(7) Effects of the Invention As described above, according to the present invention, the PNP load transistor is configured with a vertical transistor, and the word line or bit line is connected to the buried layer. By forming PNPN
In a semiconductor memory device using memory cells, the switching speed is increased and the area required for the memory cells is reduced.

[Brief explanation of the drawing]

Figure 1 is an equivalent circuit diagram of the slave memory cell, and Figure 2 is the equivalent circuit diagram of the slave memory cell.
3 is an equivalent circuit diagram showing a memory cell according to an embodiment of the present invention; FIG. 4 is a sectional view showing the physical structure of the memory cell shown in FIG. 3. ,
FIG. 5 is a cross-sectional view showing a second embodiment of the present invention, and FIG. 6 is a main circuit diagram showing a semiconductor memory device according to the present invention constructed using the memory cells shown in FIG. 4 or 5. It is. W+, W-...Word line, BL, BL...
...Bit line, MC,, MC2, MC, . ，・・・・・・
・,MCnn...Memory cell, Q,. ,Q,. '...PNP transistor for load, Q
2. , Q3. ...PNP multi-emitter transistor, Q2. ', Q3. '． ．． 、． ．． ．． NPN multi-emitter transistor. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1 A memory cell is provided at each intersection of a plurality of word lines and a plurality of bit lines, and each memory cell is provided with a PNP transistor for load and an NPN transistor constituting a flip-flop. 1. A semiconductor memory device characterized in that the load PNP transistor is formed of a vertical transistor, and the word line or the bit line is formed of a buried layer.