JPS6030134B2 - Reference frequency oscillator for phase-locked loops - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a phase-locked loop, or PLL (Pha
The purpose is to make the reference frequency output from this reference frequency oscillation method variable, etc. It was developed from.

First, an example of a phase-locked loop will be briefly explained based on Fig. 1. 1 is an antenna that receives broadcast waves, and 2 is a tuner for tuning disposed after this antenna. Then, this tuner selects a desired broadcast wave from among a large number of broadcast waves and outputs a tuning frequency signal sf.

Reference numeral 3 denotes a frequency divider arranged after the tuner 2. This frequency divider inputs the tuning frequency signal sf and divides it into a comparison signal cs of a desired frequency.

4 is a reference oscillator that outputs a reference signal ss of a desired reference frequency; 5 is a phase comparator arranged after this oscillator and the frequency divider 3; this comparator compares the comparison signal cs with the reference signal ss; Then, the phase of the comparison signal cs is equal to the reference signal s
When it deviates from the phase of s, it outputs a mismatch signal ds.

Reference numeral 6 denotes an active filter connected after the phase comparator 5. This filter inputs the mismatch signal ds, removes noise such as beats, and transmits the mismatch signal to the tuner 2.
Output to.

When the tuner 2 receives this discrepancy signal ds, it is voltage controlled and outputs a tuning frequency signal sf whose phase is tuned to the reference signal ss. In other words, the phase-locked loop shown in FIG. 1 can always output the tuning frequency signal sf in a state locked to the phase of the reference signal ss. Conventionally, this type of device has been used to tune the oscillation frequency of the local oscillator of the tuner by adjusting a variable capacitor connected in series or parallel to the crystal oscillator of the A reference frequency oscillator 4, or by adjusting the variable capacitor connected in series or in parallel with the crystal resonator of the A reference frequency oscillator 4. Is it possible to use a variable frequency divider in the frequency division stage (not shown) from the reference frequency oscillation stage 4 to the input of the phase comparator 5? A method such as applying the output of the voltage controlled oscillator 4 to a pulse swallowing counter is used.

However, A has problems in terms of stability and automatic adjustment, B has a relatively large tuning range of the output frequency of the voltage controlled oscillator 4, and C requires a dedicated integrated circuit. There were various problems such as. The present invention was developed for the purpose of solving the above-mentioned problems. First, an embodiment will be described based on the accompanying drawings. Reference numeral 21 denotes a crystal oscillator, and this oscillator outputs a signal with a frequency f.

Reference numeral 22 denotes a frequency divider connected after the crystal oscillator 21. For example, this frequency divider outputs a signal of frequency n2 in response to an input of frequency n2.

Reference numeral 23 denotes a gate circuit for switching frequencies Na, .

24 is a counter; this counter inputs and counts the signal of frequency 2 that comes through the frequency divider 22 and the AND gate 232, and sends this counting signal to the coincidence detection circuit 25 in the subsequent stage.
Output to.

26 is a presettable up/down counter, and this counter is configured to, for example, set the number of pulses N. is set in advance using the "preset input", and this set signal is
It is output to the coincidence detection circuit 25 at the subsequent stage.

The coincidence detection circuit 25 outputs the detection signal ds2 through the AND gate 231 and the inverter when the count value of the signal pulses of frequency 2 from the counter 24 matches the preset number of pulses N. gate 2
32, respectively.

27 is a frequency divider connected after the crystal oscillator 21;
This frequency divider outputs a signal with frequency N a, in other words, a constant time T as one cycle.

28 is a one-shot multivibrator connected after the frequency divider 27, and this pipelator sends a reset pulse to the counter 24 at the rising edge of the frequency limit a.
and output to the coincidence detection circuit 25, respectively.

In the present invention having the above-mentioned configuration, the output of the crystal oscillator 21 is frequency-divided by a fixed divider 22 to create a frequency of 2.

Initially, the coincidence detection circuit 25 outputs a low level as ds2 in FIG. 3 because the outputs of the counters 24 and 26 do not match. ", /Na2 switching gate circuit 23 is Na2
This output is counted up by the counter 24. The count continues to count up, and when it matches the preset value N, the output ship 2 of the match detection circuit 25
becomes high level, and the switching gate circuit 23 of Na,/〆2 passes the pulse of Na,. On the other hand, "," is counted by the fixed frequency divider 27 until a certain time T is reached.When the time T reaches, the coincidence detection circuit 25 is reset by the one-shot multiviprator circuit 28 and outputs a low level again. The counter 24 is also reset,
Na 2 to N. Start counting. The counter 26 can thus vary the pulses N and N2 that exist during a certain period of time T, thus making it possible to tune the frequency. Note that the fixed frequency divider 29 is a fixed frequency divider for lowering the composite output "o" of the switching gate circuit 23 to the frequency of the phase comparator 5.

Furthermore, when one pulse is input to the up input of the presettable up/down counter 26, the preset value N,
When 2 more pulses of 11 are input, the preset value N
. The reset input is for outputting the original preset value N. from the counter 26 when there is a pulse input.

As described above, the present invention performs tuning of the phase-locked loop system by digitally changing the frequency of the signal of the reference frequency SS applied to the phase comparator 5 of the phase-locked loop.

Therefore, it is possible to digitally vary the frequency while maintaining the frequency stability that is an advantage of the phase-locked loop, in other words, while maintaining the accuracy of the crystal oscillator 21. Specifically, within a certain time span T, count and synthesize N2 pulses and N2 pulses (see Figure 3), and set the value of N in a presettable manner. By changing, the total number of pulses N=N, 10N2 of a constant span T can be changed.

That is, there is an advantage that the frequency of the reference frequency SS can be changed very slightly. Note that the time T may be taken as long as it is an integral multiple of the phase comparison frequency SS, but if it is not, a beat will occur, but this beat will be removed by the active filter 6.

Furthermore, in the embodiment, the explanation was made using two types of frequencies, 〆, 〆2, Na 2, etc., but the more types there are, ``Na, ``, 〆2, Na 3, etc., the better. can be done.

FIG. 4 is a specific wiring diagram of the block diagram in FIG. 2, and the reference numbers in the diagram correspond to those in FIG.
...The first prize is the specific product name of the integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a block wiring diagram of a phase-locked loop circuit using an embodiment of the present invention, FIG. 2 is a block wiring diagram explaining an embodiment of the present invention, and FIG. 3 is a time chart explaining FIG. 2. , FIG. 4 is a wiring diagram embodying FIG. 2. 5: Phase comparator, SS: Reference frequency, Na,: Oscillation frequency, Na2: Frequency, T: Time (span), 21: Crystal oscillator, 22: Frequency divider, {27: Frequency divider, 28: One Short multivibrator} reset signal generating means, 24:
Counter, 23: Functional gate circuit, {25: Coincidence detection circuit, 26: Presettable counter} Coincidence detection means. Figure 1 Figure 2 Figure 3 Figure 3

Claims (1)

[Claims] 1 a reference oscillator that generates a first frequency signal;
frequency signal, which causes the lower frequency second frequency signal to be input.
a frequency divider that outputs a frequency signal of the first frequency signal; a reset signal generating means that outputs a reset signal having a constant period based on the first frequency signal; a counter that counts frequency signals and outputs a numerical signal; a coincidence detection means that outputs a detection signal when the numerical signal inputted with a specified numerical value matches the prescribed numerical value; 1 frequency signal and the second frequency signal are input, and the second frequency signal is outputted to the counter according to the detection signal, and the first frequency signal and the second frequency signal are outputted to the counter according to the detection signal. 1. A reference frequency oscillator for a phase lock loop, further comprising a switching gate means for alternately and sequentially taking out two frequency signals and outputting the same as a reference frequency for the phase lock loop.