JPS6030137B2 - Binary code converter - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a conversion device for converting a binary code consisting of, for example, 6 bits or 8 bits into a code of at least two or more digits consisting of an IG number, a character, a code, or a combination thereof. The present invention will be described below assuming that the binary code is 6 bits and the code to be converted is 2 digits. In FIG. 1, 1 is a latch circuit that stores a binary code to be converted, and 2 is a logic gate that receives the high-order digits of the binary code, that is, Z and digit bits.For example, as shown in FIG. It consists of 4 inverters and 4 NAND gates. 3 is a 4-bit binary adder which doubles each bit of the binary code except for the mebit and adds them together. 4 is a counter which inputs the 5-bit output of the adder 3; 5 is a pulse generator that adds 1 to the counter 4 after the second digit post-conversion code is read; 6 to 9 are 8 bits each 32 Flea writable read-only memory (Pro
grammableRead OnlyMemosa,P
-ROM), each of which is a two-digit code consisting of numbers, letters, codes, or a combination thereof, and stores a single carp code in consecutive addresses. Further, the memory devices 6 to 9 use the output of the counter 4 as an address designation input, and each energizing input terminal CE terminal is connected to the logic gate 2.
are connected to each output end of the 1 River and each memory device 3 to 6 1
This memory receives the output of each digit and stores it using the clock pulse from the pulse generator 11. Let us now convert the binary code into a two-digit code as shown in the table below. Note that b in the table below indicates a blank. Therefore, the memory 3
As shown in FIG. 3, 16 sets of two-digit conversion codes are successively recorded every two addresses. Of course, A, 4, etc. are not stored as they are, but as corresponding 8-bit binary numbers. A case where the binary code is [000110] and the two-digit code [AB] is converted will be explained. The upper digits of these binary codes, i.e. the public and flame bits,

[00] is applied to logic gate 2, and only its output terminal CEI becomes 0. As a result, only the memory device 6 is energized and becomes operational. Since the input bit to the adder 3 is [0110], these bits are doubled and added, and the output becomes [01100]. This becomes the input to the memory device 6 via the counter 4, so the second digit code that is read out first indicates that it is written at address 12, and this 12-digit code is shown in Figure 3. Like [A] (the code corresponding to) is stored. After this [A] is stored in the memory 10, one is added to the counter 4 by a pulse from the pulse generator 5. As a result, the input code of the memory 6 becomes [01101], so it can be seen that the first digit code is written in the first group, and that [B] is stored here. Therefore, when this [B] is stored in the memory 9, the code [AB] is read out and [000110] is converted to [AB]. In the above description, the converted binary code is 6 bits, the conversion code is 2 digits, and the memory devices 6 to 9 are at addresses 32, but the present invention is not limited to these numbers; for example, 6 bits are used. The above binary code can also be converted and added, and in this case, it is sufficient to increase the number of input bits to the logic gate 2, as well as increase the number of memories or addresses. In addition, if the code after conversion is 3 or 4 digits, each set of converted codes is stored at every 4 addresses of each memory device 6 to 9, and the adder 3 is used to store the binary code specified by the address. All you have to do is multiply each bit by 4 and then add them together. That is, m (m=2,
When converting a 3, 4...) digit code, m=2n(
When n=1, 2, 3...), each memory device 6 to 9
m codes may be stored for each 2n address, and each bit of the binary code designated by the address may be multiplied by 2n and then added together. When 2n<m<2, m codes may be stored for each 2n+1 address in each of the memory devices 6 to 9, and each bit of the binary code designated by the address may be multiplied by 2M1 and then added. As described above, the present invention specifies in advance the address of the memory where each set of m-digit codes after conversion is stored consecutively by the number of lower digit bits of the binary code, and then Since it is designed to read and convert (m-1) pieces of data for each address, it is possible to convert binary codes to characters, codes, or combinations of these, including binary IG Hayabusa conversion. At the same time, the configuration and method for this purpose are also very simple.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the device of the present invention, and FIG.
The figure is a block diagram showing an example of a logic gate constituting the specifying means of the present invention, and FIG. 3 is a schematic diagram showing the storage contents of the storage means. In the figure, 1 is a latch circuit, 2 is a logic gate, 3 is a full adder, 4 is a counter, 5 and 11 are pulse generators, 6-
9 is a storage device, and 10 is a memory. Next drawing diagram 2 drawings

Claims (1)

[Claims] 1 In a device that converts a binary code into a code consisting of m (m = 2, 3, 4, ...) digit numbers, characters, codes, or a combination thereof, each set of m converted codes is When = 2^n (n = 1, 2, 3, ...), it stores each 2^n address, and when 2^n<m<2^n^+^1, it stores every 2^n^+^1 address. a plurality of storage means, a designating means for receiving a predetermined number of high-order bits of the binary code to be converted, and selecting and designating one of the storage means in accordance with the predetermined number of bits; Each bit of the binary code to be converted, excluding the input bit to the means, is multiplied by 2^n when m=2^n, and by 2^n^ when 2^n<m<2^n^+^1. an adding means that multiplies by +^1 and then adds; a counting means that takes the output of the adding means as an input and specifies an address in the storage means; and a pulse is sent to the counting means every time an output is generated from the storage means. A binary code conversion device comprising: pulse generating means for applying (m-1) times; and a memory for storing m codes outputted from the storage means.