JPS6030446B2 - High-speed writing digital automatic gain control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high speed digital automatic gain control circuit.

Generally, an automatic gain control circuit (hereinafter referred to as "AGC") automatically changes the gain, or amplification factor, of an input signal.
It produces an output signal having a substantially constant output level.

AGC can be used in a number of systems, such as modems (hereinafter referred to as "modems"). The conventional technology uses a large number of analog A
Including GC.

However, prior art analog AGC has several inherent problems. For example, the closed loop characteristics of analog AGC are sensitive to noise, and analog AGC tends to have stability problems.
Furthermore, analog AGCs are typically driven by devices such as field effect transistors, which are inherently nonlinear, have considerable variation between devices, and have a limited dynamic range. There is. One of the most important problems with analog AGC is that it is a relatively slow write response device.

That is, after the AGC starts operating, it takes a relatively long start-up period before the appropriate gain can be selected. For example, the start-up period for analog AGC is about 250 milliseconds, and for some applications this delay can be tolerated. However, in the field of data communications, AOCs with fast write response characteristics are most desired. Therefore,
An object of the present invention is to provide an analog AGC that can solve the problems of the analog AGC described above.

Because the analog AGC of the present invention has fast write response characteristics, it requires a start-up period of only about 2.5 mm sand.
The configuration of the present invention is summarized as follows.

In the digital AGC of the present invention, the gain can be adjusted to any of a large number of discrete values in a large number of gain adjustment steps, and the AGC can adjust the gain to any of a large number of discrete values in a large number of gain adjustment steps. It has a state. Therefore, by setting the digital AGC to a certain state, one corresponding gain out of a plurality of gain values can be obtained. The digital AGC is configured to receive an input signal and generate an output signal that is a function of the input signal and a gain of the digital AGC. The input signal is still in an unmodulated analog state during the start-up period.

In steady state, the input signal is typically a suitably modulated analog signal containing the information to be conveyed. In order to drive the digital AGC, the A
Means is provided for initially setting the gain of the GC to an initial value. The gain adjustment signal is generated in response to an output signal representing the level of the selected gain value. Means responsive to the gain control signal is provided in the digital AGC to cause at least one gain adjustment step to adjust the gain value of the digital AGC to a higher or lower value in response to the gain control signal. The digital AG
Although C is used in the same way in the starting state as in the steady state, it is advantageous if it is controlled in one way in the starting state and in another way in the steady state.

The digital AGC is controlled by a gain adjustment or gain control signal, and the gain adjustment signal or gain control signal represents the level of the gain, but does not represent the level of the gain itself. . This allows the cost of the digital AGC circuit to be reduced and the structure to be simplified. The gain adjustment signal can be created in a variety of different ways.

For example, in one example, an analog-to-digital converter can sample an analog output signal to generate multiple digital samples. The output level of the selected number of digital samples is compared to a reference level. Therefore, the comparator generates a gain adjustment signal representing the level of gain. To reduce the length of the start-up period, more of the discrete values of gain are passed through in the first gain adjustment step than in subsequent gain adjustment steps.

For example, if the gain value is fixed at 1 needle, the first gain adjustment step is from the gain value "8" to the gain value "12''.
and the second gain adjustment step is a gain value of “1”.
2'' to a gain value of ``14''. Regarding the number of passed gain values, the number of gain values for a given gain value is controlled by making each subsequent gain adjustment step smaller in size than the previous gain adjustment step. By executing
It will be reached instantly. In this case, even though the gain adjustment signal does not provide information on the magnitude of the gain error. However, it should be noted that the final gain adjustment step is of the same size as the immediately preceding gain adjustment step. It is not necessarily necessary that the gain be adjusted much in the first gain adjustment step, even though many of the discrete values of gain are passed through.

This is because the AGC gain value does not need to be defined on a linear scale, but rather the scale is logarithmically non-linear. In order to further reduce the starting period, the initial value of the gain value is preferably set as follows.

That is, approximately half of the discrete values of the gain are set larger than the initial value, and approximately half of the discrete values are set smaller than the initial value. Note that this does not necessarily mean that the initial gain is half of the maximum gain, since the scale determined by the gain value does not need to be linear. In a preferred embodiment, the digital AGC has 2N gain values and N gain adjustment steps are required to complete the start-up sequence.

Furthermore, if possible, it is desirable that the digital AGC has logarithmic characteristics. Each gain value is then X decibels apart, where X is any fixed value greater than zero. The logarithmic AGC is beneficial because it will be logarithmically proportional to the gain. Although various variations on the above concept are possible, the digital AGC advantageously comprises a large number of switches and means responsive to the state of the switches for selecting a gain value. be.

In such a configuration, each of the multiple states of the nuclear switch group will correspond to one gain value. When the switch group is activated, the initial state of the switch group is set by means to generate the initial gain value.

The switches are then actuated appropriately to effect the gain adjustment step. For example, the initial gain value may be set such that the first switch is opened or closed depending on the initial gain value, and the second switch is changed regardless of the initial gain value. When used,
The digital AGC circuit has means responsive to gain-related characteristics of its output signal. This operation changes the gain from the initial value to the second value. Thereafter, by opening or opening the second switch according to the level of the second gain value and changing the state of the switch shown in FIG. 3, the gain changes to the third value. be. When the switch group is driven in this manner, only N switch groups are required to select a predetermined one from 2N gain values.

Furthermore, to select one of the 2N gain values,
A maximum of N executions are required. For example, if an analog-to-digital converter generates 9,60 solid samples per second, and 4 or 5 samples are used to determine high or low gain, the above can be accomplished quickly. Become. At steady state, the gain adjustment step is typically smaller than during the start-up period.

For example, during steady state following the startup period, the AG
The C setting is increased or decreased by one value at a time.
In addition, the opportunity to change the gain in steady state is based on the average value of a large number of signal samples, which allows decisions to be made based on the average value of a small number of signal samples as if they were made during the start-up period. In addition, it is possible to prevent the effects of noise amplification that would otherwise occur if this was done subsequently. Embodiments of the present invention will be specifically described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the digital AGC circuit device of the present invention.

In FIG. 1, a digital AGC circuit device 11 includes a digital AGC 13, an analog-to-digital converter 15, and a processor 17. If necessary, a bandpass filter can be provided between the digital AGC 13 and the analog-to-digital converter 15. Since the digital AGC circuit device 11 is particularly used in a modem receiver, the embodiments of the present invention will be described in terms of its application to a modem. However, it goes without saying that the digital AGC circuit device 11 is also suitable for other uses. The digital AGC13 is Ana.

The analog-to-digital converter 15 receives an input signal and generates an output signal. The output signal is a function of the input signal and the selected gain value of the AGC 13. During the start-up period, the input signal is an unmodulated analog signal, and in steady state is a double-sided, carrier-suppressed, quadrature amplitude modulated signal. The digital AG
C13 has a number of independent individual gain values by which it is possible to multiply the input signal and provide an output signal to the analog-to-digital converter 15.

Any gain value can be used,
Determine whether this gain value is on a linear scale or a non-linear scale. In the description of this embodiment, it is assumed that there are eight gain values, and each of these values has a difference of 1 decibel from adjacent values.

The analog-digital converter 15 is the AGC 13
The analog output signal is sampled from the analog output signal to generate a digital signal consisting of digital samples.

The digital signal is then given to the processor 7. That Anna. A digital converter 15 samples the analog output signal at a desired rate, eg, 9,600 samples per second. The processor 17 measures the output of the digital signal and compares the measured value with a reference value.
For example, the four or five digital samples generated by the analog-to-digital converter 15 are averaged and used to determine the output of the incoming digital signal. As a result of this comparison, the gain adjustment signal is
Respective groups of sample values are generated by the processor 17 to represent that the gain has increased or decreased. The gain adjustment signal need not provide information about the magnitude of the error in the gain. Regarding the gain adjustment signal, the processor 17
3 to adjust the gain values in a predetermined order as described below. Although FIG. 2 shows an example of the digital AGC 13, it is clear that the invention is not limited to this.

In FIG. 2, the digital AGC 13 consists of a resistance switching circuit, that is, three switches 9, 21, and 23;
It has a 2-needle zone or 8 different gain values. Of course, the number of switches 19, 21, 23 and the number of different gain values can be selected depending on actual requirements.
The switches 19, 21, 23 are preferably electronic switches, for example transistors, transistor circuits or junction field effect transistors. In this embodiment, it is desirable that the digital AGC 13 provide high gain and reduce the quantization noise of the analog-to-digital converter 15.

In other words, it is desirable that the output signal of the digital AGC 13 has a large signal value compared to the quantization step. However, the output signal must not exceed the dynamic range of the analog-to-digital converter 15. This condition sets the upper and lower limits of the output signal to an acceptable output signal level and allows selecting the correct number of switches for the dynamic range of the analog-to-digital converter 15.
In this example, each of the eight different gain values are 1 dB apart. The digital AGC 13, which is composed of one integrated circuit, has two amplifiers 25 and 27.

The amplifiers 25 and 27 are operational amplifiers having the same or different gains. The amplifier 25 has two parallel input paths including resistors 29 and 31, respectively, and a parallel member return path including resistors 33 and 35, respectively. The switches 19 and 21 are connected in series with resistors 31 and 35, respectively. An input signal is applied to the negative input terminal of the amplifier 25 by a conductor 36 connecting the input path and the negative feedback path to the negative input terminal. The other input terminal of the amplifier 25 is grounded. The output signal of the amplifier 25 is applied to the negative input of the amplifier 7 through a parallel input path.

The parallel input paths include resistors 37 and 39, respectively, and the resistor 39
The switch 23 is connected in series with the switch 23. The positive input terminal of the amplifier 27 is grounded and the output signal is applied to the parallel input path of the amplifier 27 by means of a feedback path comprising a resistor 41. In the embodiment shown in FIG.
The output of the digital AGC 13 becomes an output signal applied to the analog-digital converter 15.
It is possible to use any desired number of amplification stages. Each gain value of the digital AGC 13 is determined by a resistor 29.
, 31, 33, 35, 37, 39, and 41, and the gains of the amplifiers 25 and 27. These selections can be easily made by one skilled in the art, and the resulting gain values can be suitable for any use of the AGC. As described above, each gain value can be determined on a linear scale or a non-linear scale, so in this embodiment, these gains are determined on a logarithmic scale. The digital AGC 1 3 is the switch 1
By operating 9, 21, and 23, any separate gain value can be driven.

For example, Table 1 below shows the relationship between the gain values and the states of the switches 19, 21, 23, where the symbol "
1” indicates that the switch is open, and the code “0” indicates that the switch is open.
” indicates that the switch is involved. As is clear from Table 1 and FIG. 1, the digital AGC 13 is controlled by the processor 17.

FIG. 2 shows a detailed example of the control means of the AGC 13, which will be explained below. The digital sample value from the analog-to-digital converter 15 is determined by the value obtained from the read-only memory (ROM) 47.
They are multiplied separately in multipliers 43 and 45. Especially the R
The OM 47 generates two sets of coefficients, each of which cycles periodically and is 90° out of phase. The digital sample values are multiplied by two sets of coefficients from the ROM 47 in agenda counters 43 and 45, respectively. One set of coefficients are the sine values of three equally spaced angles, for example 1200, 2400, and 3600, and the other coefficients are the cosine values of these angles.

During the start-up period, this multiplication process generates a voltage vector in the real and imaginary channels to represent the power level of the output signal from the AGC 13.

On the other hand, in a steady state, for example, U.S. Pat.
, 996, the modulated signal from the AGC 1 3 is non-coherently demodulated by this multiplication process. The carrier frequency and sampling rate can, of course, be changed depending on the desired result; for example, in this embodiment, the carrier frequency is 1600 Hz and the sampling rate is 6,400 days2. The voltage vectors from multipliers 43, 45 are sent through real channel 48 and imaginary channel 48a, respectively, for processing by the modem receiver.

These voltage vectors are summed by squaring circuits 49, 51, and the squared values are summed by adder 53 to generate a value proportional to the power of the output signal from AGC 13. In particular, the power of the output signal of the AGC 13 is proportional to the sum of the arbitrary values of the voltage vectors in the real channel and the imaginary channel. Since this is a well known method of determining power level, no further explanation will be given below. For accurate power measurements, the adder preferably averages the sum of the squares of the voltage vectors from a large number of samples.

Therefore, in this embodiment, the adder 53 is provided to average the sum of the arbitrary values of the voltage vectors obtained by four or five consecutive digital samples of the analog-to-digital converter 15. A signal representing this average value is sent to one terminal of the comparator 55, and the adder 5
Sent by 3. The comparator 55 is connected to the adder 5
3 is compared with a constant reference value representing a predetermined power level. The comparator 55 then compares the actual average power level measured by the four or five consecutive digital sample values with a predetermined power level and, depending on the result, inputs a digital value into a successive approximation register (SAR) 57. Generates a gain adjustment signal. The SAR57 may be, for example, model DM2503 manufactured by National Semiconductor Corporation of Santa Clara, Calif., USA. In this example, the gain adjustment signal represents only the sign of the comparison. In other words, the information included in the gain adjustment signal is only information that represents the level of power of the output signal of the digital AGC 13. The SAR 57 responds to the gain adjustment signal during the start-up period by switching the switch 19.
, 21, 23, thereby controlling the state of digital A
Controls the gain of GC13.

SAR 57 is connected to receive the gain adjustment signal from comparator 55 and also has a number of output terminal bits. Three of the output terminals are connected to the switches 19, 21, 23 via a multiplexer 65 that controls the switches 19, 21, 23, respectively. The digital AGC 13 has an inverter 59 that inverts the output of the SAR 57 to control the switch 21. Switches 19, 21, 23 are digital AGC1
Although the gain of 3 is controlled according to various different programs to suitably adjust the gain of 3, this control is preferably
This should be done in accordance with the flowcharts shown in FIGS. 3 and 4. When the start signal is applied, multiplexer 65 will be set to forward only the signal introduced from SAR 57, and adder 53 will put itself into a mode in which it averages only a relatively small number of its inputs. . Additionally, SAR 57 will set all bits to zero as a result of switches 19 and 23 being opened, and switch 21 will be closed by inverter 59. The SAR 57 defines bit n as the most important bit for controlling the switch 19, and sets bit n to state "1".
”. As a result, the switches 19, 21, 2
The bit controlling 3 is in state "1-0-10", switches 19 and 21 are closed and switch 23 is engaged. The "1-0-0" state represents binary 4 and corresponds to an initial gain of 4 as shown in the diagram of FIG. 4 and the table above. Therefore, about half of the gain values are larger than the initial value;
Also, about half of the gain values are smaller than the initial values. Once drive begins, the power of the output signal from the digital AGC 13 is measured as described in connection with FIG. 2, instead of the first set of samples from the converter 15.

The comparator 55 determines whether the power is high or low, and the SAR
57 to generate a gain adjustment signal. Since the gain adjustment signal has only two states, the state where the measured power corresponds to the desired power is treated as a high power state. If the power is high, the SAR57 will
The gain is decreased by resetting bit n to the "0" state so that the gain can be achieved. If the power is low, SAR 57 will not reset bit n and switch 19 will remain closed. And the 6AR5
7 determines whether all bits have been tested, and if not, yields AR57 considers the next most significant bit to be n. Furthermore, the SAR57 is
Regardless of whether the power from previous measurements was too high or too low, a bit is set that controls the switch 21 to the "1" state. This opens switch 21.
In this start-up procedure, when one gain adjustment step is performed, switch 19 is opened and closed according to the previous power measurement, and the switches 21 and 23 are opened and closed regardless of the previous power measurement.

In other words, referring to FIG. 4, the switches 19 and 2
The bits controlling 1 and 23 are in the “0-1-0” state or the “1-1-0” state, and the gain is “2” or “6”.
It is. The process of power measurement and determining whether the power is high or low and whether all bits have been tested is repeated to obtain a second set of samples from the converter 15. This is discussed above and shown in FIG.
The second sample group may be four or five samples generated subsequent to the first sample group, with a digital sample not used for power measurement interposed between the two sample groups. In this embodiment, there are no samples that are not used for power measurement between the first and second sample groups. At high power, the bit controlling switch 21 is reset to the "0" state, allowing switch 21 to open. If the power is low, the switch 21
remains open. The bit controlling switch 23 is set to the "1" state regardless of whether the power is high or low, closing switch 23. At this time, the switches 19, 2
The state 1 is due to the first and second measurement results, respectively, and the switch 23 is closed regardless of the previous power measurement. Thus, as shown in FIG. 4, the bits controlling the switches 19, 21, 23 are in one of the following states. In other words, “0-0-1” “0-1-1”
“1-0-1”''1-1-1”.And the gain is one of the following values: “1”, “3”, “5””
7". During the start-up procedure, a second gain adjustment step is carried out, and as is clear from FIG. 4, the second gain adjustment step is:
It is smaller than the first gain adjustment step.

In particular, the first gain adjustment step changes from the gain value "4" to "
The second gain adjustment step is gain adjustment from the gain value "2" or "6" to plus "1" to minus "1". The power measurement and decision process to determine whether all bits have been tested
5 to obtain a third group of samples.

For high power, the bit controlling switch 23 is
It is reset to "0" to open the switch 23, reducing the gain. If the power is low, the bit is not reset and the gain is left unchanged. In this state, the third gain adjustment step is performed. The gain is set to any value from "0" to "7" as shown in FIG. SAR 57 determines whether all three bits have been tested and relinquishes control of the digital AGC 13, as explained in detail below. Following each power measurement, the bit being tested is reset or not reset depending on the result of the power measurement, and the next bit in the bit string is set to the "1" state.

Further, following this, any of the 2N gains is selected by performing N times, even if no information about the gain error amount is given. Once the start-up procedure is completed and the gains are set appropriately as described above, the digital AGC may be controlled during steady state in one of several different ways.

The SAR 57 applies a bit test end signal to the multiplexer 65, up/down counter 67, and adder 53 through conductors 61, 63, and 64, respectively. In response to the bit test end signal, the multiplexer 65:
This is the output signal from the SAR 57 and the switch 19, 2.
1, 23 is no longer transferred, and the signals from the up/down counter 67 to the switches 19, 21, 2 are no longer transferred.
3 control signals will be transferred. Meanwhile, in response to the bit test end signal, the up/down counter 67 is introduced with the switch control information contained in the SAR 57. Further, the bit test end signal causes the adder 53 to
is a mode that averages a large number of voltage vectors and generates an output signal. For example, each signal from the adder 53 may be based on four or five samples during the start-up period.
Then, in steady state, each output signal from the adder 53 will be based on 1,000 samples. The output signal from adder 53, based on a large number of digital samples, is introduced into a pair of comparators 69,71.

The comparators 69 and 71 compare this output signal with a countdown threshold value and a countup threshold value, respectively. The countdown threshold is sharper than the countup threshold. If the signal from the adder 53 is greater than or equal to the countdown threshold, the comparator 69 generates a signal to the up/down counter 67 instructing the counter 67 to count down. Similarly, the comparator 71 determines that if the signal of the adder 53 is below the count-up threshold,
A signal instructing the counter 67 to count up is generated to the up/down counter 67.
When the signal from the adder 53 is between the two threshold values applied to the comparators 69 and 71, no signal is applied to the up/down counter 67, and the state is maintained. In response to each count up signal of the comparator 71, the up/down counter 67 generates an output signal that increases the gain of the digital AGC 13 by "1".

For example, if the gain of the AGCI 13 is "4", which corresponds to the state in which the bits controlling the switches 19, 21, and 23 are "11010", the counter 67 controls these switches. The switch 23 is closed in order to generate a binary "5" in which the controlling bit is in the state of "1-0-1", thereby obtaining a gain of "5". Similarly, in response to each countdown signal of the comparator 69, the counter 67 sets the gain of the AGC 13 to "1".
decrease only. For example, from gain “4” to gain “3”
”, the counter 67 generates a digital value “3” or “0-1-1” state at its output, thereby changing the state of both switches 21, 23 to the gain value “ 3". Functionally speaking, the control of the AGC 13 in the steady state differs from the control of the AGC 13 in the start-up state in two ways.

First of all, in the steady state the gain increases or decreases by a value of "1" at a time, but in the starting state, at least for some frequency adjustment steps, the gain increases or decreases by a value of "1" at a time. Change. Furthermore, the gain adjustment steps performed during the start-up period are tapering, whereas the gain adjustment steps performed during steady state are of equal magnitude. Then the second
The advantage is that the gain adjustment steps performed in steady state are based on a larger number of samples than during the start-up period. Although the present invention has been described in detail with reference to one embodiment, it is obvious to those skilled in the art that the present invention can be implemented in other embodiments.

Therefore, the technical scope of the present invention should be determined only by the claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a digital AGC circuit according to an embodiment of the present invention.
Fig. 2 is a more detailed block diagram of the digital AGC shown in Fig. 1, Fig. 3 is a flowchart showing the driving method of the digital AGC, and Fig. 4 is a method of selecting an appropriate gain during the start-up period of the ACC. FIG.

1 3. ．．・．． ．． ．． Digital AGC, 1 5...
...Analog-digital converter, 17"""processor, 19,21,23...Switch, 47...
...ROM, 49,51...square circuit, 53...
Adder, 55, 69, 71...Comparator,
57... Continuous approximation register (SAR), 65...
...Multiplexer (MUX), 67...Up-down counter.

Figure/Figure ~ ship Figure 3 child diagram

Claims (1)

[Claims] 1: a digital automatic gain control circuit having a plurality of gain values for receiving an analog input signal and generating an analog output signal that is a function of the analog input signal and the selected gain value; an analog-to-digital converter for sampling an analog output signal from the converter and generating a digital signal consisting of digital samples; a multiplication process for calculating a voltage vector from the digital signal of the analog-to-digital converter; A first output signal is generated by averaging a small number of voltage vectors, and a second output signal is generated by averaging a large number of voltage vectors of the multiplication process during steady state.
power level determining means for generating an output signal; a first comparator for comparing a first output signal of the power level determining means with a constant reference value and generating a digital gain adjustment signal according to the comparison result; a continuous approximation register into which a gain adjustment signal is input; a second comparator that outputs a countdown instruction signal if the second output signal of the power level determining means is equal to or greater than a countdown threshold; and a second output signal of the power level determining means. a third comparator that outputs a count-up instruction signal if the count-up instruction signal is less than a count-up threshold, and an up-down counter that counts down or counts up according to the count-down instruction signal of the second comparator or the count-up instruction signal of the third comparator. , a multiplexer that transfers a control signal from the continuous approximation register to the digital automatic gain control circuit during a start-up period and transfers a control signal from the up-down counter to the digital automatic gain control circuit during a steady state; A high-speed writing type digital automatic gain control circuit, characterized in that the digital automatic gain control circuit is configured to change a gain value by a control signal from the multiplexer.