JPS6030447B2 - automatic gain control circuit - Google Patents

Description

[Detailed description of the invention] The present invention relates to automatic gain control circuits.

Automatic gain control circuit, so-called AGC (Au matjc
GainControl) circuits are widely used as circuits for compensating for signal level fluctuations.

For example, in a typical voice or data transmission system,
A pilot signal is inserted into an appropriate frequency band of these transmission signals and transmitted, and the receiving system applies AGC to the transmission signal using the level fluctuation of the pilot signal as an index.
This is usually called P (Pilot)-AGC. By the way, in the receiving system using P-AGC, the level fluctuation of the pilot signal is used as an indicator, so if the pilot signal disappears or the level drops due to some reason, such as a failure of the pilot signal generator or a failure of the repeater in the transmission system. In this case, the receiving system tries to increase the transmission signal to the maximum level even though it is at a normal level. A memory function is added as an effective means to prevent such malfunctions. This memory function stores the previous normal pilot signal level when a pilot signal abnormality is detected by the pilot signal level determination means, and uses this retained pilot signal level to simulate the transmission signal level. During this time, maintenance personnel are issued a warning to prompt them to take appropriate measures. As for this memory function, conventional CR
It includes a time constant circuit, and the voltage charged in an extremely large capacitor C is used as the pilot signal level just before that to be held.

However, since the holding time is required for 5 to 6 hours or more, special parts are required for the capacitor C or high impedance element R, and these C,
A special method such as a completely sealed low-temperature container is required as a mounting means for R. This has resulted in various drawbacks such as an increase in the size of the circuit. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an automatic gain control circuit which can eliminate the above-mentioned disadvantages.

In accordance with the above object, the present invention provides a digital memory means for sequentially retaining level fluctuations of a pilot signal in the form of a digital signal, and when the pilot signal is abnormal, the level fluctuation of the pilot signal corresponding to the level immediately before the abnormality is supplied from the digital memory means. It is characterized in that the gain of an automatic variable gain amplifier, etc. is maintained using DC voltage or current. The present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing a general P-AGC circuit.

In this figure, Sin is the input transmission signal and Sout is P-
This is the output transmission signal with AGC added. Signal Sin is first input to variable equalization circuit EQLII. Variable equalization circuit 1
1 adds a predetermined loss to the signal Sin by using, for example, a thermistor as a variable element. Further, in the hybrid circuit 12, the signal is divided into two parts, and only the pilot signal is extracted by the bandpass filter 13. The extracted pilot signal is amplified by the control amplifier 14, and then the level fluctuation is extracted by the detector 15. In the initial stage of P-AGC, the level fluctuation of the pilot signal from the detector 15 is directly released to the variable element in the variable equalization circuit 11 via lines L and C, and AGC is performed. was.

However, in this case, when the pilot signal is disconnected or the level drops, the loss of the variable equalizer circuit 11 decreases rapidly, and even if the input level of the transmission signal Sin is normal, the output level suddenly increases, resulting in an abnormal state. Therefore, we decided to add a memory function. This memory function includes a comparator COM16, a CR circuit 17, a switch 18-1,
It is composed of 18-2 mag. When the pilot signal is normal, both switches 18-1 and 18-2 are at the upper contact point in the figure, and the level fluctuations of the pilot signal are sequentially held in the CR circuit 17 and simultaneously applied to the variable equalization circuit 11. be done. If the pilot signal is disconnected or the signal goes down, the comparator 16 detects this and switches both the switches 18-1 and 18-2 to the lower side in the figure. As a result, the variable equalization circuit 11 is supplied with a DC voltage or current equivalent to the previous pilot signal level charged in the capacitor C, and the signal Sin
This avoids the inconvenient situation of a sudden change in the situation. However, the general P-AGC shown in this figure has problems with the various drawbacks described above. Therefore, the present invention is directed to the P-AG shown in FIG.
C circuit and eliminates its drawbacks.

In FIG. 2, the same reference numerals or symbols as in FIG. 1 indicate the same components. The gist of the present invention is to always digitally track the level fluctuations of a pilot signal, and to hold this in a digital memory means, so that when the pilot signal is disconnected or the level is down, the voltage immediately before being supplied from the digital memory means is This is to maintain the loss or gain of the controlled circuit at a DC voltage or current equivalent to the pilot signal level. In this figure,
The pilot signal level from the detector 15 is added to one input of the comparator 21 as an input Pin. Input Pin
The movement with respect to the elapsed time t is as shown in FIG. 3A, for example. The output of comparator 21 is applied to the U/D control input of up/down counter 23, which
As long as the /D control input is logic "1", the quack signal from the oscillator 25 is passed through the AND gate 24 to its C
Continue to receive on the LK input. Therefore, the count value of the counter 23 continues to increase. Then, when the output Pout obtained by converting the counted value into analog in the digital-to-analog D/A converter 22 matches the above-mentioned Pin, the comparator 2
1 outputs a logic "0", and the counter 23 counts down this time. In any case, the output Pout continues to follow the input Pin at the cycle of the clock signal. The change in the output Pout with respect to the elapsed time t is as shown in FIG. 3B. Eventually, the level fluctuation of the pilot signal is supplied to the variable equalization circuit 11 in the form of Pout as shown in FIG. 3B, and AGC is applied thereto. Here, suppose that the pilot signal is interrupted or the bell-down occurs (see time T in FIGS. 3A and 3B).

Accordingly, the comparator 16' outputs the logic "
1" to logic "0". Therefore, the AND gate 24 is closed and the clock signal from the oscillator 5 is no longer supplied to the counter 23. Therefore, the counter 23
continues to hold the final count value, ie, the count value immediately before said time T, no matter what logic is applied to its U/D control input. At this time, the count value just before the pig UT is shown as a constant value CPout in FIG. 38, and this is the output P of the digital/analog converter 22. ut, the gain of the variable equalization circuit 11 is controlled to be constant after time T, and it is possible to prevent the level of the signal S;n from becoming excessive. At this time, the output Pin of the wave detector 15 is approximately zero as shown in FIG. 3A. As explained above, according to the present invention, 1. The conventional P
-AGC can be executed as is, 2.

By introducing the clock signal, the response speed to the pilot signal can be varied by changing the frequency of the clock signal.
3 It can be realized in the form 4 with commercially available inexpensive IC parts.

For example, as for the digital/analog converter, its function is simply to make Pin follow Pout, so there is almost no problem with accuracy, and an inexpensive one can be used. Furthermore, an automatic gain control circuit is realized which has various advantages such as the ability to branch off the output of the oscillator 25 from an existing one in the terminal station and to omit the oscillator 25.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a general P-AGC circuit, FIG. 2 is a block diagram showing an embodiment of the P-AGC circuit based on the present invention, and FIGS. 3A and 3B are the same as those shown in FIG. It is a graph for illustrating waveforms of Pin and Pout. In the figure, 21 is a comparator, 22 is a digital/analog converter, 23 is an up/down counter, 25 is an oscillator, Sin is an input transmission signal, Sout is an output transmission signal with automatic gain control, and Pin is a received pilot signal. ,
Pout is a pilot signal formed according to the present invention. Figure 1 Figure 2 Figure 3A Figure 3B

Claims (1)

[Claims] 1. A variable equalization circuit that receives an input transmission signal including a pilot signal and applies gain control, and a hybrid circuit that branches the output from the variable equalization circuit into two and sends one output as an output transmission signal. An automatic gain control circuit added to the hybrid circuit extracts the pilot signal having a level fluctuation from the output of the other branched into two by the hybrid circuit, and includes a comparator which takes the pilot signal as one input. An up/down counter that uses the output of the comparator as an up/down control input and a clock signal as a counting input, and a digital/analog converter connected to the counting output of the up/down counter are provided. The output of the analog converter is used as the other input of the comparator and the gain control input of the variable equalizer circuit, and the clock signal monitors the level fluctuation to detect an abnormality in the pilot signal. An automatic gain control circuit characterized in that the automatic gain control circuit is turned off when an abnormality in the pilot signal is detected by a comparator.