JPS6030975B2 - Error detection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error detection method for a data processing device, and in particular, the present invention simplifies the circuit and identifies whether an error occurs in an input circuit and an output circuit or in another circuit. Regarding the error detection method that can be used.

A parity detection method is widely used as an error detection method for conventional data processing devices.

This method uses parity as a check bit in the input data.
By adding bits and inputting the data to a data processing device and checking the output of the processing device, it is possible to detect whether an error has occurred in the processing device. However, with this method,
It is not possible to distinguish whether the error occurred in a data processing circuit directly involved in data processing in the processing device or in an input/output circuit such as a register or driver located before or after the data processing circuit. Therefore, in order to identify whether an error occurs in the data processing circuit, the input circuit, or the output circuit, an error detection method as shown in FIG. 1 has conventionally been used.

In the figure, 1 is a write data register as an example of an input circuit, 2 is a data processing circuit, 3 is a read data register as an example of an output circuit, 4 is a parity generation circuit, 5 is a parity check circuit, and 6 is a parity check circuit. A parity generation circuit and 7 are a parity check circuit. Now, when 8-bit write data WDo to WD7 are input, these are input to the parity generation circuit 4.
After a parity bit Po is added to the data, the data is temporarily stored in write data register 1.

Then, by applying the data write clock WCLK to the write data register 1, the write data WDo to WD
7 is sent from the write data register 1 to a data processing circuit 2, such as a storage element. At the same time WDo
WD7 to WD7 and Po undergo a parity check by the parity check circuit 5. If an error is detected as a result of this parity check, the parity check circuit 5 generates a write data parity error signal WOPE. Further, when data is read from the data processing circuit 2, the read data is temporarily stored in the read data register 3 with a parity bit P added thereto by the parity generation circuit 6. and data read clock RCL
When K is applied to the read data register 3, the read data is applied to the parity check circuit 7 together with the parity bit P and subjected to a parity check, and the read data RDo to RD7 are output to the outside. Become. At this time, if an error is detected, the parity check circuit 7 generates a read data parity error signal RDPE. In the conventional system, as described above, by providing a parity generation circuit and a parity check circuit in the input circuit and the output circuit, respectively, it is possible to identify errors in the input circuit and the output circuit.

However, such a system inevitably complicates the entire device.

Furthermore, unless the data processing circuit is operated to provide data to the output circuit, it is not possible to detect errors in the output circuit. SUMMARY OF THE INVENTION An object of the present invention is to provide a method that eliminates the above drawbacks and can easily separate errors in data processing circuits and data input/output circuits.

Another object of the present invention is to provide a method for detecting errors in an input/output circuit without operating a data processing circuit, and for this purpose, data to be processed is input. In a data processing device having an input circuit, a data processing circuit that processes the input data, and an output circuit that outputs the data processed by the data processing circuit, an error detection code is attached based on the input data. a first data holding means for temporarily holding input data; a parity generation checking circuit for generating a parity bit and performing a parity check; and a first data holding means for temporarily holding output data of the data processing device. The present invention is characterized in that it is possible to test the input circuit and/or the output circuit by providing a second data holding means and a testing means for testing the data held in the second data holding means.

An embodiment of the error detection method of the present invention will be described below with reference to FIG.

In the figure, the same reference numerals as in FIG. 1 indicate the same parts, 8 is a storage element as an example of a data processing circuit, and 9 is a parity generation/check circuit that generates a parity bit and performs a parity check.

Now, in FIG. 2, when 8-bit write data WDo to WD7 are transmitted, the write data WD.

After being given a parity bit P2 by the parity generation circuit 4, WD7 to WD7 are stored in the write data register 1 together with the parity bit P2. Then, when the data write clock WCLK is applied to the write data register, the write data WDo to WD7 are sent out from the write data register together with the parity bit P2. The write data WDo to WD7 are then transmitted to the storage element 8. At the same time, the write data WDo to WD7 are transmitted to the parity generation/check circuit 9 together with the parity bit P2 by commonly connecting the input/output terminals of the storage element 8, and subjected to a parity check. The parity generation/check circuit 9 is comprised of exclusive OR circuits 10 to 17, as shown in FIG.

The write data WDo to WD7 are now “00000000”.
'', and when using even parity, the parity bit P2 provided by the parity generation circuit 4 is logic ``0''.

Therefore, each input terminal Do of the exclusion OR circuit 10 to 13 constituting the parity generation check circuit 9
A logic "0" is input to D7 through D7, and a logic "0" is also input to the parity bit terminal Po. Therefore, in this case, the exclusive OR circuit 17
, the logic "01" will be output, and the parity
Logic "1" is never output to the error signal PERR. However, a failure has occurred in the write data register 1 and the input data transmission circuit, and the write data WDo
For example, even though "00000000" is input as WD7, the output is "00000001".
If so, the parity generation/check circuit 9 receives a logic "1" only at its input terminal D7, and receives a logic "0" at the other input terminals.

Therefore, exclusive OR circuits 13, 15, 1
6 outputs a logic "1", so the exclusive OR circuit 17 also outputs a logic "1", that is, a parity error signal PERR. In this way, it becomes possible to detect that an error has occurred in the data input circuit system. Furthermore, when the write data WDo to WD7 are output from the write data register and transmitted to the memory element 8, if a write pulse is applied to the memory element 3, the write data WDo to WD7 can be transferred to the memory element 8. Can be written to 8.

Then, when reading the data stored in the memory element 8, the read data RDo to RD7 are outputted from the memory element 8 and applied to the input terminals Do to D7 of the parity generation and inspection circuit 9. be done. Therefore, if the read data RDo to RD7 are "00000001", logic "1" is applied only to the input terminal D7 of the parity generation/check circuit 9, and logic "0" is applied to the input terminals Do to D6. will be done. In this way, the exclusive OR circuits 13, 15, and 16 output logic "1", and among these, the logic "1" output from the exclusive OR circuit 16 corresponds to the read data RDo to RD.
It will be given as parity bit P3 for 7. Note that the parity generation detection circuit 9 is configured such that the logic "1" is output from the exclusive OR circuit 17 at this time, but the signal at this time does not act as the parity error signal PERR. . Thus, the data RD mysteriously revealed from memory element 8
o through RD7 are transmitted to extracted data register 3 along with parity bit P3.

Then, the read data register 3 receives a successive clock signal RCL.
If K is applied, the parity check circuit 7 will check the parity.
A check is performed, and if an error has occurred in the input data register 3 or the output data transmission circuit, the parity
An error signal PERR is generated from the parity check circuit 7, but if there is no error, the read data RDo to RD
7 can be output from the parity check circuit 7 to the outside. As described above, in the present invention shown in FIG. RD7 to RD7 can be operated as a parity generation circuit.

Therefore, compared to the device shown in FIG. 1, the configuration can be simplified. In the above description, an example has been described in which a memory element is used as a data processing circuit, but of course the present invention is not limited to only a memory element as a data processing circuit.

For example, in FIG. 2, 8 is considered to be a general data processing circuit, that is, a general data processing circuit that processes input data and outputs it.

In this case, as described above, the input data is given parity bit P2 by the parity generation circuit 4, passes through the write data register 1, undergoes a parity check by the parity generation check circuit 9, and at the same time the input data is Processed by the data processing circuit 8. After the data has been processed, it is output from the data processing circuit 8. At this time, the output data is transmitted to the parity generation/check circuit 9 and a parity bit P3 is added thereto. The data then passes through the reminder data register 3 and undergoes a parity check by the parity check circuit 7. In the above case, the explanation is when the data processing circuit 8 is operated and input data is processed, but the data processing circuit 8 is in a no-operation state, that is, the input data is passed through without being processed. It is possible to operate even in situations where Next, a case will be described in which the data processing circuit 8 is used in a no-operation state.

When input data is applied, parity bit P2 is given by parity generation circuit 4, and the input data and parity bit are stored in write data register 1, and as in the case described above, data write is performed. A clock WCLK is applied to the write data register to transmit the input data and parity bit to the parity generation/check circuit 9 for parity checking.

At this time, the input data is also applied to the data processing circuit 8, but since the data processing circuit 8 is in a no-operation state, the input data passes through the data processing circuit 8 as is. The input data that has passed through the data processing circuit 8 is transmitted to the parity generation and check circuit 9, and the parity generation and check circuit 9 generates a parity bit P2 accordingly.

This parity bit P3 is stored in the read data register 3 together with the input data that has passed through the data processing circuit 8. When the data read clock RCLK is applied to the read data register 3, the input data and parity bit P3 are transmitted to the parity check circuit 7 and subjected to a parity check. As explained above, the second
In the embodiment shown in the figure, whether the data processing circuit 8 is in an operation state or a no-operation state, it is checked whether an error has occurred in the input circuit or the output circuit. can do.

After all, according to the present invention, it is possible to reduce the number of parity generation and checking circuits compared to the conventional one, and the input/output circuit can be checked without operating the data processing circuit, and the overall configuration is simple. , it is possible to obtain an error detection method in a data processing device that can identify an error source.

[Brief explanation of drawings]

FIG. 1 shows a conventional error detection system, FIG. 2 shows an embodiment of the present invention, and FIG. 3 shows a parity generation/check circuit. In the figure, 1 is a write data register, 2 is a data processing circuit such as a storage element, 3 is a read data register, 4 is a parity generation circuit, 5 is a parity check circuit, 6 is a parity generation circuit, and 7 is a parity check. circuit; 8 is a data processing circuit such as a memory element; 9 is a parity generation/check circuit; 10 to 1;
7 is an exclusive OR circuit. Evening 1 figure Ki 2 figure Old figure 3

Claims (1)

[Claims] 1. In a data processing device having an input circuit into which data to be processed is input, a data processing circuit into which the input data is processed, and an output circuit into which data processed by the data processing circuit is output, an error detection code generation circuit that applies an error detection code based on the input data; a first data holding means that temporarily holds input data; a parity generation check circuit that generates a parity bit and performs a parity check; a second data holding means for temporarily holding output data of the device;
An error detection method characterized in that an input circuit and/or an output circuit can be tested by providing a test means for testing data held in the second data holding means.