JPS6031038B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, particularly a dynamic random access memory (RAM) provided with redundant word lines.

In order to provide redundant bits in a memory, a method of providing a redundant word line, a method of providing a redundant bit line, and others can be considered, but providing a redundant word line in a dynamic RAM poses a problem in terms of access time.

Considering the cell selection operation, this first requires RAS (low
The CAS (column address strobe) is output and the row (word line) address is fetched, clock generation, word line selection, sense amplifier activation, etc. are then output, and the column (bit line) address is fetched. A column line is selected, a memory cell is accessed, and so on, with row selection being done first. Therefore, when providing a redundant word line, in the conventional method, it is first determined whether the input row address is a defective address or not, and then the word line is selected, and the access time is reduced by the time required for this determination. It becomes big. The present invention attempts to improve this point by using redundant bits of the dynamic RAM as redundant word lines, without particularly affecting the access time.

The purpose of this is to attach a redundant word line with static memory cells to a cell array in which dynamic memory cells are arranged in a matrix, and to use a column decode signal for the cell array to correspond to one of the static memory cells. Further, a defective address matching circuit is provided in which a defective word line address is written in advance and outputs a signal when the address signal of the defective word line is input. The redundant word line functions as a column input/output line for inputting/outputting the storage information of the static memory cell selected by the column decode signal, and the normal side and redundant side column input/output lines have gates switched by the output of the matching circuit. The output and write buffers are connected to each other. This will be explained in detail below with reference to the illustrated embodiments. FIG. 1 shows an embodiment of the present invention applied to a transistor type dynamic RAM.

In the figure, W is a word line, B is a bit line, and a dynamic memory cell DM is provided at each intersection of these lines. Cell DM is a one-transistor type, and is composed of a MOS transistor Q and a capacitor C. One end of each pair of bit lines B is connected to sense amplifier SA, and the other end is commonly connected to input/output lines 1, 12 to output buffer OB and write buffer WB via transistors Q and Q3. . The cell DMo connected to one of the pair of bit lines B and B leading to the sense amplifier SA is a dummy cell. Transistor Q interposed in bit line B
2 is a gate that is turned on and off by the output of the column decoder CD. W' is a redundant word line, and a static memory cell SM is provided at the intersection with each column. The cell SM includes driver transistors Q, Q3, a load L, and gate transistors Q, Q? The transistors Q and Q7 are turned on and off by the output of the column decoder CD. This redundant word line W', which also serves as a column input/output line, is used for writing via transistors Q and output buffers WB,
Connected to OB. These transistors Q, Q8, Q
, Q3 are opened and closed by the outputs P and P of the defective address matching circuit COMP.
The address of the defective word line in the normal word line group W is compared with the lower address RA input when selecting a cell, and if they match, the output is set to P (P is set to L). However, during the judgment operation time of the coincidence circuit COMP, the outputs P, (
P) is the day (L), and if it is determined that the row address RA is not a defective address, the day (L) is maintained as it is.
With the above configuration, when an address is given at the timing shown in FIG. 2, the operation is as follows.

Addresses are given in the order of row address R, column address CA, and reading is performed using the row address strobe RA.
S, column address strobe CAS is set to L. When the row address RA is taken in, addressing A is started, and then the potential of the corresponding word line W is increased based on the address RA. During this time, the coincidence circuit COMP is in the discrimination operation, and the output P is low. Therefore, transistor Q3 is on,
Transistor Q3 is off. When the potential of the regular word line W becomes low, the sense amplifier SA is activated by the clock LE, and one of the pair of bit lines is set to high and the other is set to low depending on the storage contents of the memory cell. That is, as is well known, in this one-track cell type memory, the bit line is pre-charged to the potential V when picking up the bowl, and the dummy cell D has a capacitance of 1'2 of the real cell DM, so the real cell is stored with the stored information "1". When a dummy cell is charged to voltage V, there is no change in the potential of the line even if the cell is selected and connected to the bit line.On the other hand, when a dummy cell that has been discharged due to reset is connected to the bit line, the potential of the line changes. In response to this, the sense amplifier SM consisting of a flip-flop turns off (day level) on the real cell side and turns on (low level) on the dummy cell side, but since the potential change is small, a predetermined value is required for this. It takes time. Real cell D with memory content “0”
When M is uncharged, the bit line potential on the cell side drops to V2 (V. It takes time. When this stage is finished, the column address CA is taken in, but by that point the coincidence circuit C
The judgment operation of the OMP has been completed, and the outputs P, , P have taken values of either day or L depending on the judgment result. Second
The figure shows a case where a defective address is input, and P and P are inverted. Therefore, the column decoder CD generates an output and gate transistors Q2, Q2, Q6, Q? When turning on, the logical output of the normal side memory cell (in this example, this is the error output) is given to the input/output lines 1, 12, but it is blocked by the gates Q3 and Q3 and is not sent to the output buffer OB. Instead, the output of the redundant memory cell SM passes through gates Q and Q8 and is input to the output buffer OB. If the row address RA is a good address, P becomes H and P becomes L, transistor Q3 is on and Q8 is off, so data is read from the real cell DM side as usual.Memory cell SM is a static type. Therefore, when transistors Q7 and Q are turned on, the voltage L is fixed, and when these transistors are turned on, the potential of the column input/output line W' increases rapidly, which is due to the dynamic memory cell DM. This is equivalent to the state in which the sense amplifier SA has completed its operation.

Therefore, even if the row address RA is a defective address, there is no delay in data output. If this redundant memory cell SM is of a dynamic type, a sense amplifier SA is required, and the time required for the redundant memory cell SM to change to either LOW or LOW is added, slowing down the operation. As described above, according to the present invention, defective address judgment is started in parallel with row addressing, and before starting column addressing, normal and redundant memory
Since the J cells are switched and the redundant word line is configured with a static memory cell group, there is no delay caused by the sense amplifier, and access time equivalent to that of a dynamic RAM without a redundant word line can be obtained. There are advantages.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a time chart used to explain its operation. In the figure, DM is a dynamic memory cell, W is a normal word line, SM is a static memory cell, W' is a redundant word line, and COMP is a defective address matching circuit. Figure 1 Figure 2

Claims (1)

[Claims] 1. A redundant word line in which static type memory cells are arranged is attached to a cell array formed by arranging dynamic type memory cells in a matrix, and a column decode signal to the cell array is used to determine the correspondence among the static type memory cells. In addition, a defective address matching circuit is provided in which a defective word line address is written in advance and outputs a switching signal when the address signal of the defective word line is input. The line functions as a column input/output line for inputting/outputting the storage information of the static memory cell selected by the column decode signal, and the normal side and redundant side column input/output lines are gates switched by the output of the matching circuit. 1. A semiconductor memory device, characterized in that the device is connected to an output and a write buffer via an output buffer and a write buffer.