JPS6031108B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary field effect transistor (hereinafter referred to as C/MOS).
The present invention relates to a method of manufacturing a semiconductor device that eliminates the drawbacks caused by bipolar transistors parasitic on the semiconductor device.

Various circuits constructed using C/MOS have been known in the past, and representative examples thereof will be explained with reference to FIGS. 1 and 2.

This inverter circuit consists of P channel MOS Tr8 and N
The source electrode of 8 is connected to the positive power source Voo, the drain electrode of 8 is commonly connected to the drain electrode of 82 to form the output terminal, and the source electrode of 82 is connected to the negative power source V$. tie. Further, the gate electrodes 8 and 82 are both connected to the input terminal to form an inverter. FIG. 2 is a cross-sectional side view of this circuit formed on a semiconductor wafer.

In this example, a so-called P-well layer 2 made of an N conductivity type impurity having a concentration of about 2×1 and 6 atoms/substrate is formed on an N conductivity type substrate 1 having a concentration of about 1×1 atoms/substrate.
is formed on the N conductivity type substrate outside this P-Well layer 2.
The P regions 3 and 4 that will become the channel MOSTr (for example, 1
and 9a ms/). On the other hand, also in the P-well layer 2, N conductivity type impurities are diffused to the extent of 1 poatoms/in the N regions 5 and 6 which will become the N channel MOSTr.
Furthermore, P- and N-type diffusion regions 7 and 8 connected to a power source are formed in the P-well region 2 and the rest of the semiconductor substrate 1. Following this, approximately 1
A thin layer of silicon oxide with a thickness of 500△ is deposited, holes are formed in the necessary areas, and a circuit is connected using a semiconductor such as a mountain. If necessary, a protective film is provided on the substrate to obtain a C/MOS semiconductor device. This process is schematic and is provided as an example. In a C/MOS circuit having such a structure, the threshold/direct voltage yth of the P-channel MOSTr and the N-channel MOSTr have opposite polarities, so they all operate in the opposite direction with respect to the input voltage, and their operation is extremely unstable. small. For example, 5V for VoD,
When Vss is grounded (GND), if 15V is supplied to input ln, 02 will be conductive (ON) and 8, will be non-conductive (OF
F), and no direct current flows between VDo and V$. Therefore, C/MOS circuits generally have almost no operating power consumption, and in the pulse transient region of input information, 8, 82
Both turn on, and only an instantaneous transient current flows, a leakage current occurring in the PN junction, and a current for charging and discharging the load capacitance at the output. Therefore, generally C/M
The power of the OS circuit can be said to be extremely small. However, in such a C/MOS circuit system, there is an impu
Vo when noise is added like lse.

A phenomenon occurred in which a large DC current (several tens of mA to several hundred mA) flows between -V$ and the current continues to be maintained even after the noise is removed. The polarity of this impulse has positive and negative polarities, and in order to eliminate this phenomenon, it is necessary to lower the VoD below a certain voltage or turn off the power to the circuit system. The present invention provides a novel method for manufacturing a semiconductor device that eliminates the above-mentioned drawbacks. That is, it was completed based on the fact that it was discovered that a specific thyristor circuit is configured in a semiconductor device having a C/MOS structure.

FIG. 3 is a cross-sectional side view showing this thyristor circuit created in a C/MOS circuit, and FIG. 4 is an equivalent circuit diagram thereof.

This is made up of a plurality of bipolar transistors, and once thyristor operation occurs, the power often becomes enormous. To explain this thyristor circuit with reference to FIG. 3, an N-type semiconductor substrate 1
Parasitic bipolar transistors Tr2 and Tr4 are formed along the thickness direction of the semiconductor substrate in the P-Well region 11 formed by the river, and parasitic bipolar transistors Tr2 and Tr4 are formed in the semiconductor substrate 10 outside the P-Well region 11 in a direction crossing this thickness direction. parasitic bipolar Tr,, Tr3
In addition to the above, the resistor circuit is constituted by the P-well region 11 and the resistor held by the N-type semiconductor substrate 10. Further, N+ regions 12, 13 and P+ regions 14, 15 forming the sources and drains necessary for the C/MOS, P+ regions 16 and N+ regions 17 serving as contact regions are formed, and a guard ring layer 18 is further formed. . In the following explanation, Q is a current increase rate generally defined as a bipolar transistor term, a current increase rate defined by B'Masan7, 1
is current, and the symbols attached to 1 are e: emitter, b: base, c: collector, and the numbers or symbols mean each Tr and resistance.

As shown by the solid arrow in Fig. 4, when positive impulse noise is added to the output, the current of Q3 × lin flows into the Rp-well.
When the voltage drop becomes V2, T
A current 1 flows through the base of r2.

Ijago Q3Iin (Rp-Well>>rbe2...
...[If the collector current of lITr2 is 1, False Ni821b2ni82 is 31in...■Similarly, when 13 becomes the drive current and the voltage drop between RNsub becomes Vbe, the base current of Tr, lb , flows, and Tr is in the ON state.

lb,=lc2(RNSub>rq)...
...'3'lc,=6,lq=3,62 Q31i
n...[41 Here, in order for the current to be maintained between VDo and GND, that is, between Tr, Tr2 even if external noise is removed, lb2Sic.
...It is sufficient if the condition of t51 is satisfied.

That is, Q31in Mi8,P2 Q31in 1=Mi8,62...■ When the condition 1<8,82 is satisfied, the base current IQ(n) of one cycle is changed from the base current IQ(n) of the next one cycle.
11) becomes large, and as the current flowing through the system increases by repeating the cycle, 8 starts to decrease after reaching 6max, so it does not diverge infinitely.

That is, in a steady state, the above-mentioned abnormal current is considered to settle down when the following two conditions are satisfied. lb2(n-
1): lb2(n), 8, (n), 8(n), etc.Although the size of the Tr is not the main factor in the likelihood of the abnormal current flowing, based on the above equation, will be considered.

When we measured the current increase rate using the size of the Tr dimensions (more precisely, the drain area) as a parameter, we found that there was a correlation between the current value when the abnormal current was collected and the size of the Tr dimensions, and the drain area was large. The higher the Tr, the larger the abnormal current, and conversely, the smaller the Tr, the smaller the value. Also, even if negative noise is added to the output, lb, mi Q41in (RN
submir 戊,) ・・・・・・【7'lc,=
8, lq=8, Q41inlb2, (Rp-wel
l》r戊2) lc2:B21Q=3,82 Q41in
The conditions for maintaining the current in the system are lb,≦2 1≦8,82...■.

In order to prevent the abnormal current generated by the operation of the thyristor circuit, it is necessary to
Bipolar Tr formed along the vertical
It has been shown that it is sufficient to keep the P product of raITr to 1 or less for La formed along the main surface of the transistor and the semiconductor substrate. Next, as a concrete means to satisfy this condition, {i} expands the inside of the base.

'Reducing the lifetime of the raw semiconductor substrate and reducing the lifetime of the wafer that is the base of the semiconductor substrate 〇 Inserting a heat treatment process to shorten the lifetime of the semiconductor substrate ■ Adding Au to the semiconductor substrate It has been found that methods such as doping are effective. Regarding the river, the base medium of Vemcal Tr2 and Tr4 shown in Figure 3 is N-su.
By enlarging the distance between blo o and the N+ region 12, and further between the N-s sail 10 and the N+ region 13, and by increasing the distance between the LateralTr
, and the base of Tr3, that is, P-Well region 1 1
and the distance between the P+ area 14, the P-Wen area 11, and the P+ area 15 questions.

In Figures 5 and 6, Wv (France), WL in the base of VerticalNPNTr and La of raIPNPTr are shown.
(France), and the current increase rate hfev was plotted on the vertical axis to show its dependence on the base medium. For the current increase rate shown on the vertical axis, the maximum value among the values obtained by measurements for each base is adopted. In addition, VenjcaITr2T in FIG.
The base of r4 is substantially calculated by subtracting the depth distance of each N+ region 1 2, 1 3 from the backside silicon xi at the depth of the P-Well region 11 (that is, in the thickness direction of the semiconductor substrate). The value was shown. In addition, in FIG. 5, the slumping time of the P-Well area is changed to 20, 40, and 60 hours, and the P-Well area is
The dose amount was corrected so that the displayed concentration in the l area was constant.
On the other hand, Fig. 7 shows the product of the current increase rates of both Tr, which is 3 products, by searching for WL (1) in the base of the teraITr based on the depth distance L (France) of the P-Well region of the VemcaITr. If it is larger than 1, the abnormal current occurs;
・Sometimes it didn't happen.

However, the current increase rate shown in Figures 5 and 6 is that C/
Since its value changes depending on the PrOCeSS used to create the MOS circuit, the slope of the straight line showing the B product in Figure 7 changes.

However, by selecting the depth of the VerticaITr and the base of the teraITr, that is, the depth of the P-Well region and the base of the raITr for La, and suppressing the 8 product to 1 or less, abnormal current can be prevented.

Increasing the distance between the P-Well region 11 and the P+ regions 14 and 15 is intended to reduce the current increase rate of the LateralPNPTr, but this
The base of the NPNTr is defined by xi of the P-Well region.

However, the transport efficiency of teralPNPTr may become 0 depending on a certain base median value, so it cannot be expanded indefinitely. Late example Tr and VenjcaIT like this
By controlling WL and Wv in the base of r, it is possible to regulate the 8 product to 1 or less.

Next, some means for reducing the lifetime of the semiconductor substrate will be explained.

A specific means of this method is to set the heat treatment temperature to about 1100° C. after the step of pulling the semiconductor single crystal in order to correct the resistivity of the single crystal.

Conventionally, this type of heat treatment was performed at a temperature of about 950 oo, but by performing it at around 1100 oo,
The current increase rate of Tr and Vertical Tr is set to La.
aITr from 5×10-2 to 1.4×10-2, Ve
It was confirmed that the rtical Tr decreased from 200 to 56. The temperature range of the heat treatment process mentioned above is 1000 oo~
115000 is possible and 1050qo~1150q0
is quite effective and 1100qo is the best.

Next, the method described above is carried out after the gate oxidation step in the C/MOS manufacturing process.

This C/MOS process is generally carried out as follows. After depositing the oxide on the semiconductor substrate, apply PE to the desired location.
After removal using the P method, impurities are diffused into the exposed semiconductor substrate to form source and drain regions. Of course this sauce,
In addition to the drain region, a diffusion region is created as described above. In order to form a gate electrode between the source and drain regions, the oxide in the portion corresponding to this region is removed and then a thin oxide is deposited on the exposed semiconductor substrate. (Hereinafter, this step will be abbreviated as an oxidation step.) After this step, the semiconductor substrate was heat-treated at 120,000 ℃ for 1 minute.

After implementing this process, perform the same process as before, and then
When the current increase rate of eraITr and VenicaITr was measured, VemcaITr2Tr4 without the heat treatment showed a value of 200, whereas that of VemcaITr2Tr4 without the heat treatment process showed a value of 50LateralTr. In T. et al., 5×1 pi was reduced to 1.4×10-2, and it was extremely effective. Next, we will discuss the pairing method. After the gate oxidation process, the oxide adhering to the back side of the semiconductor substrate, that is, the area where circuit elements are not formed, is removed, and an etching process is performed to clean this area. Remove the substrate.

Next, gold is deposited to a thickness of about 300A. A gold wire with a diameter of 1 is used as the evaporation source, and the temperature of the object to be evaporated, that is, the semiconductor substrate, is set at room temperature. After the vapor deposition process is completed, the temperature is 1100℃.
After holding in N2 for 10 minutes, proceed to the secondary process.

The C/MOS circuit obtained by inserting this process is Vert.
The current increase rate of icalTr was as shown in FIG. In this figure, the horizontal axis shows the heating time after vapor deposition, and the vertical axis shows the ratio of the current increase rate when doping with gold to that when there is no gold diffusion. As can be seen from this figure, the current increase rate decreases as the gold diffuses, indicating that it is effective.
This gold diffusion creates a vertical Tr inside the parasitic Tr.
eraITr and P MisakiTr>npnTr.

In this way, the present invention solves the problem of parasitic T formed in C/MOSTr.
By controlling the 8 product of r to be less than 1, it is possible to prevent abnormal current from occurring, which is extremely practical.

[Brief Description of the Drawings] Fig. 1 is a C/MOS circuit diagram of a subsidiary, Fig. 2 is a cross-sectional side view of the circuit shown in Fig. 1 created on a semiconductor substrate, and Fig. 3 is a cross-sectional view of a semiconductor substrate according to the present invention. The side view, Fig. 4 is an equivalent circuit diagram of a thyristor circuit formed in a C/MOS circuit element, and Fig. 5 is a V
Figure 6 shows the dependence of the current increase rate hfev on the base, with the base of the erticalTr as the axis, and the current increase rate on the vertical axis. 7 is a diagram showing the relationship between the base of both parasitic transistors and the 8 product of both transistors, and FIG. 8 is a diagram showing the relationship between the current increase rate depending on the presence or absence of gold diffusion. In the figure, 10: semiconductor substrate, 11: well region, Tr,, Tr3: parasitics are teraITr, Tr2, T
r4: Parasitic Ve9icaITr. Figure 1 Figure 2 Figure 3 Figure 5 Figure 4 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] 1. An impurity region of a second conductivity type is formed in a semiconductor substrate of a first conductivity type, a MOS type transistor having a channel of a second conductivity type is formed in the semiconductor substrate outside the impurity region, and a first impurity region is formed in the impurity region. In a method for manufacturing a semiconductor device forming a MOS type Tr having a channel of a conductivity type, after the step of pulling a semiconductor single crystal serving as a base of the semiconductor substrate, 1
1. A method for manufacturing a semiconductor device, comprising a heat treatment step at 000°C to 1150°C.