JPS6031109B2 - Semiconductor device and its manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device that enables high integration and a method for manufacturing the same.

When impurities are diffused into a semiconductor substrate in the manufacturing process of an integrated circuit device, the extent of diffusion at a corner greatly depends on the ratio of the surface concentration of the impurity diffusion layer to the impurity concentration of the semiconductor substrate.

This is particularly noticeable in the corner portion recessed inside the P-well diffusion layer in the CMOS (complementary MOS) process. FIG. 1a is a plan view showing the diffusion profile at the corner of the P-well, in which 1 is an N-type semiconductor substrate, 2 is a P-well region, and 3 is a P-well formed on the substrate 1.
In the + region, the region 3 is, for example, the source or drain of a P-channel MOS transistor.

What should be noted in FIG. 1 is that xj (the boundary between the N and p regions) protrudes abnormally at the inwardly recessed corner of the P-well region 2. That is, the mask (resist, oxide film, etc.) 4 and P-well for forming the P+ region 3 are used without paying any attention to the corner portion.
When a pattern is drawn with the distance from the mask 5 for forming the P-well region 2 being L, if the ratio of the surface impurity concentration of the P-well region 2 to the impurity concentration of the substrate 1 becomes large, the corner At the side sufficiently far away from the
Although there is a sufficient distance from the edge of J to the edge of xi of P-well region 2, it almost disappears at the corner, and the distance of P-
A punch-through phenomenon occurs between the well region 2 and the P+ region 3. In other words, in the past, in order to maintain the punch-through withstand voltage at the corner portion, a sufficient margin was provided for the distance L, making it difficult to miniaturize the integrated circuit. Moreover, in some cases, the above-mentioned problems occur at corner portions. A first object of the present invention is to prevent punch-through that occurs at the corner portion of a diffusion region in a semiconductor device requiring a high degree of integration without taking a margin. The purpose of this is to prevent punch-through occurring at the corner portions without increasing the impurity concentration of the substrate, in other words, without reducing the ratio of impurity concentrations between the substrate and the diffusion layer.The third objective is to further An object of the present invention is to provide a semiconductor device that can achieve high integration and a method for manufacturing the same.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a pattern plan view showing the same embodiment, but since this example corresponds to the one in FIG. Explain the characteristics. That is, as shown in FIG. 2, the corner portions of the P-well mask 5 are shaped to protrude inside the P-well region 2. Of course, this shape is not limited to a rectangular shape, but may be circular or the like. If a mask with convex portions 11 provided at the corner portions is used as described above, the P-well region 2
xj is corrected and becomes sufficiently concave even at the corner, and even if the distance between the P-well mask and the P-well mask is much longer than L, and is -, the P+ at the corner is
A sufficient distance between the xj end and the P-well xj end can be secured,
There is no need to worry about the punch-through phenomenon. This means that
The same holds true even if the method shown in FIG. 3 is used. That is, the P-well mask 5 shown in FIG. 3a and the mask 12 having holes 13 shown in FIG. A phosphorus diffusion process is added to cancel out the diffusion in the corners, that is, the P-well diffusion. The process of obtaining the configuration shown in Fig. 3c is as follows:
．． 0×1 and 5 skin-3) 1 is prepared, oxidation process of the wafer, photo-etching process to obtain mask 5, OP-wel
Ion (boron) implantation step (dose amount 1) to obtain l region 2
．． 0x1 and 3-2), (i) photo-etching process to obtain the mask 12, ion (phosphorus) implantation process from the N hole 13, (g) slumping process (1200°C), and photo-etching process to obtain the mask 4; The steps are performed in the order of the P+ diffusion step to obtain the skin P10 region 3. FIG. 4 is a pattern plan view showing another embodiment of the present invention.

That is, the feature of this embodiment is that the corner portion 21 of the P10 region 3 has a shape in which the corner is obliquely notched. To obtain this shape, a mask 4 having the same shape may be used. If the procedure is as shown in FIGS. 2 to 4, the substrate impurity concentration NB=1.0×1 and 5-3 or 2.
By using the same manufacturing process as before, even for semiconductor wafers with 0x1 and -3 of 5c, P-we
The distance between the corner parts of the ll region 2 and r region 3 can be increased, that is, the distance between P-well xi and Px xi can be made uniform for both the corner part and the side part. Punch-through in between can be completely prevented.

In other words, the distance between the P+ mask 4 and the P-well mask 5 can be shortened, which is very effective in miniaturizing integrated circuits. Note that the impurity introduction step for obtaining the P-well region 2 and the P-well region 3 may be either ion implantation or diffusion. 5 to 7 show modified examples of the embodiment shown in FIG. 4, and FIG.
The figure also shows an example in which the corner part is cut into a rectangular shape, and FIG. By making the shape, the one side and the P-well
The distance between the side of the area 2 and the other part of the area 3 adjacent to the corner of the P-well area 3 and the P-well area 2 is
This is an example of a case where the distance is greater than the distance between the sides of the .

FIG. 8 shows a different embodiment of the present invention, in which the corner portion has an N
This is an example of a case where a + region 31 is formed to ensure a sufficient distance between P-wenxi and rxi.

To obtain the configuration shown in FIG. 8, P + diffusion using a mask 4 as shown in FIG.
Although N+ diffusion using a mask that exposes only the area to be formed in 1 may be performed separately, P+ diffusion using a mask that does not have the corner portions notched and N+ diffusion with a higher concentration than the above diffusion may be performed separately. It is also possible to provide an N1 region 31 in the section and cut out at the corner of the region 3. In this case, the timing for providing the N+ region 31 may be before or after the timing for providing the P+ region 3;
+ It is desirable to do this at the same time as diffusion. Further, it is preferable that the depth of the N+ region 31 is the same as or deeper than that of the region 3. FIGS. 9 to 12 show modified examples of the embodiment shown in FIG. 8, and FIG. 10 is an example in which the shape of the N+ area 31 at the corner part is cut out to include the corner part of the P+ area 3 and extend to the adjacent side on one side of the corner part, and the shape of the N+ area 31 at the corner part is made into a square. For example, in FIG. 11, the N0 area 31 in FIG.
FIG. 12 is an example in which the N+ region 31 in FIG. 10 is extended beyond the corner of the P-well.

FIGS. 13 and 14 show further different embodiments of the present invention.

That is, the punch-through phenomenon that conventionally occurs at the corners of the P-well region is caused by the corners being at right angles, and the more acute the angles of the corners, the worse the condition becomes. Therefore, the looser the angle of the corner, the better the condition will be. Figure 13 follows this idea, and the angle of the corner part of the P-well mask 5 and the corresponding angle of the P-ten mask 4 are made gentler, while Figure 14 shows the angle made rounder. . 1. Next, let's talk about the P-we with CMOS configuration.
Although this example was applied to the ll process, it can also be applied to the n-well process, and can also be applied to boundary corners when a p-well region and an n-well region are placed adjacent to each other on a low concentration substrate, as well as bipolar integrated circuits, etc. Various applications are possible, such as being applicable to countermeasures for the corners of the P and N regions. As explained above, according to the present invention, the first region of the second conductivity type (for example, P-well region) formed on the semiconductor substrate of the first conductivity type, and the second region of the second conductivity type formed on the substrate. It is possible to prevent the boundary between the second region (for example, the P+ region) from coming too close to each other at the corner, and therefore, it is possible to prevent the punch-through phenomenon that has conventionally tended to occur.

Furthermore, since the overall separation distance between the first region end and the second region end, which was conventionally provided to prevent punch-through, can be reduced, the degree of integration can be improved. Conventionally, in order to prevent the punch-through problem, it has been considered to increase the concentration of the semiconductor substrate and narrow the concentration range standards, and the supply of such silicon wafers has been called for, but the necessity of this has been , since the shape of the first region can be reshaped with respect to the second region, it is completely eliminated.
Therefore, in the semiconductor device to which the present invention is applied, the range of use of the wafer can be relaxed, and the semiconductor device can be made at low cost.

[Brief explanation of the drawing]

Figure 1a is a plan view showing the diffusion profile at the P-well corner of a conventional CMOS device, Figure b is a sectional view taken along line B-B in Figure a, and Figure 2 shows the problems with the device. A pattern plan view of the improved P-well corner part,
Figures 3a and 3b are plan views of mask patterns that improve the problems of the same device, and Figure 3c is a P-we obtained using the same mask.
FIG. 4 is a pattern plan view of a P-well corner portion according to an embodiment of the present invention, and FIGS. 5 to 14 are pattern plan views showing different embodiments of the present invention. be. 1... N type substrate, 2... P-well region, 3... r region, 4... P+ mask, 5...
... P-well mask, 21 ... corner portion, 31 ... N+ region. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 9 Figure 6 Figure 7 Figure 8 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14

Claims (1)

[Scope of Claims] 1. A semiconductor substrate of a first conductivity type; a first region of a second conductivity type provided on the substrate and having an inwardly recessed corner portion;
The corner portion provided on the base body includes a second region of a second conductivity type opposite to the corner portion near the corner portion recessed inside the first region, and the first region facing the first region,
A semiconductor device characterized in that a notch is provided in at least one corner of the second region. 2. By making the first side of the second region adjacent to the corner of the second region into a cutout shape that includes the corner of the second region, the first side and the first Claim 1, wherein the distance between the sides of the area is greater than the distance between the second side adjacent to the corner of the second area and the side of the first area. The semiconductor device described in . 3. The semiconductor device according to claim 1, wherein the notch shape of the corner portion of the second region is a shape in which the corner is cut off diagonally. 4. The semiconductor device according to claim 1, wherein the cutout shape of the corner portion of the second region is a rounded corner shape. 5. The semiconductor device according to claim 1, wherein the notch shape of the corner portion of the second region is a shape in which the corner is cut off into a rectangular shape. 6 a first conductivity type semiconductor substrate; a second conductivity type first region provided on the substrate and having an inwardly recessed corner portion;
A second corner portion provided on the base body and facing the corner portion near the corner portion that is recessed inside the first region.
a conductive type second region, and a notch is provided in at least one corner of the opposing first and second regions, the semiconductor device being formed in the base body. In the method of manufacturing a semiconductor device, the first region is formed by introducing impurities into the base using a mask having a shape of the first region having a notch shape at a corner portion. 7 a first conductivity type semiconductor substrate; a second conductivity type first region provided on the substrate and having an inwardly recessed corner portion;
A second corner portion provided on the base body and facing the corner portion near the corner portion that is recessed inside the first region.
a conductive type second region, and a notch is provided in at least one corner of the opposing first and second regions, the semiconductor device being formed in the base body. In the method of manufacturing a semiconductor device, the second region is formed by introducing an impurity into the base using a mask having a shape of the second region having a notch shape at a corner portion. 8 a first conductivity type semiconductor substrate; a second conductivity type first region provided on the substrate and having an inwardly recessed corner portion;
A second corner portion provided on the base body and facing the corner portion near the corner portion that is recessed inside the first region.
a conductive type second region, and a notch is provided in at least one corner of the opposing first and second regions, the semiconductor device being formed in the base body. 1. A method of manufacturing a semiconductor device, comprising implanting impurities of a first conductivity type into at least corner portions of the second region where the notches are formed. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the impurity of the second conductivity type is implanted into the notch forming portion so as to have a higher impurity concentration than the second region. 10. The method of manufacturing a semiconductor device according to claim 8, wherein the impurity is implanted by ion implantation. 11. The method of manufacturing a semiconductor device according to claim 8, wherein the impurity is implanted by diffusion.