JPS6031283B2 - Gate circuit for electronic musical instruments - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate circuit for an electronic musical instrument, and more particularly to a gate circuit that does not generate a direct current fluctuation component, so-called vedestal, and is highly suitable for integration into an integrated circuit.

Various types of gate circuits have been proposed for electronic musical instruments, but in any case, one that does not generate vedestal is desired.

For conventional examples of such gate circuits and their improvements, see
It is described in detail in Japanese Unexamined Patent Publication No. 1376/1983.

Here, the description will be explained using FIGS. 1 and 2. FIG. 1 shows a conventional gate circuit in which no vedestal occurs, and FIG. 2 shows its operating waveform diagram. In FIG. 1, T and T2 are both switching transistors,
A control signal Vs is applied to its base from a control terminal 2. The respective emitters of transistors T and T2 are connected to resistors 4 and 5.
and grounded through. The collectors of transistors T and T2 are connected to the input and output terminals of a current amplifier 6, respectively. The current amplifier 6 includes a diode-connected transistor T3 and a grounded emitter transistor T4.
It is composed of a current mirror circuit, but its mirror gain is doubled. Therefore, when a current 1 is drawn from the collector of the transistor T3, that is, the input terminal of the current amplifier 6, a current 21, twice that amount, flows out from the collector of the transistor T4, that is, the output terminal of the current amplifier 6. An output terminal 3 is provided at the connection point between the collectors of the transistors T and T2. Further, a scale signal voltage source 1 is connected to the emitter of the transistor T. In the above configuration, when the control voltage Vs is applied to the control terminal 2, the transistor T allows a maximum current of 1 to flow according to the magnitude of the control voltage Vs, but the scale signal voltage source 1
opens and closes the transistor T, so that its current is intermittent depending on the scale signal frequency.

This intermittent current is amplified twice by the current amplifier 6, resulting in a current waveform such as 21 in FIG.
It flows out from 4. On the other hand, the transistor T2 conducts a current 12 determined by a resistor 5 having a resistance value equal to that of the resistor 4. Therefore, the output terminal 3 has an output current 1 of (21.-12). flows out. The average value of this current becomes 0 at any point in time of the control signal Vs, so no vedestal occurs. Although the gate circuit shown in FIG. 1 is excellent in eliminating the vedestal, it has the following drawbacks.

First, since the pulse signal is directly applied to the emitter of transistor T, the pulse signal is differentiated and transmitted to the collector of transistor T through the emitter-collector capacitance.

This coupling exists even when the base voltage Vs becomes OV and transistors T and T2 are cut off.

Therefore, the differential waveform of the input pulse signal always leaks to the output terminal 3. Therefore, when this is used as a gate circuit for an electronic musical instrument, a small "chee" sound is generated even though no keys are pressed. Next, there is a problem when integrating it into an integrated circuit.

First, resistors 4 and 5 typically occupy a larger area within an integrated circuit than transistors. Therefore, in order to realize integrated circuits, it is desirable to have a gate circuit that does not require such a resistor. Further, power consumption occurs in the resistor 4. Generally, integrated circuits for electronic musical instruments often use gate circuits, so such power consumption increases the temperature of the integrated circuit and reduces its reliability. Moreover, such power consumption is completely wasteful, and is therefore undesirable in the case of battery drive. The present invention eliminates these conventional drawbacks and provides a gate circuit for an electronic musical instrument that is configured to be suitable for large-scale integration.

An embodiment of the present invention will be described below with reference to FIG. The embodiment shown in FIG. 3 is intended to be implemented as a complementary MOS integrated circuit. MOS field effect transistors (hereinafter simply referred to as FETs) Q, to Q6 constitute one gate circuit, and FETs Q, . ~Q, 6 constitutes another gate circuit. FETQ, ~Q4 are n-channel type, FET
ET false, Q6 is p-channel type. FETQ, and Q
2 each source is connected to ground E and each drain is connected to a FET
It is connected to each source of Q3 and Q4, respectively. FE
Each drain of TQ3 and Q4 is connected to each drain of FETQ and Q6. Each source of FETQ and bulb is connected to the power supply V
Connected to cc. A control signal Vs is applied to both the gates of FETQ and Q4. Gates of FETQ and Q6 and F
The drains of ETQ5 are connected together. An output terminal is drawn out from the connection point between the drains of FETQ and Q. FET
The backgates of Q, .about.Q4 become the substrates of n-channel transistors, or p-wells, in integrated circuits.

The back gates of FETs Q5 and Q6 are connected to power supply Vcc. This back gate becomes the substrate portion of P-channel transistors Q5 and Q6 in the integrated circuit. FETQ, . ~Q, 6 is also connected in the same way as the above gate.

Another control signal V,s is applied to the gates of FETQ,3 and Q,4.
are connected, and other output terminals are drawn out from the connection points of FETs Q, 4, Q, and 6. 10 and 11 are T flip-flops, which sequentially convert the scale signal applied to the input terminal 9 into 1
/Divide the frequency by 2.

T flippf. Output A of pin 10 is applied to the gate of FETQ. The output B of the T flip-flop 11 is F
ETQ,. is applied to the gate of If the T flip-flops 10 and 11 are also formed into complementary MOS circuits using FETs, they can be conveniently integrated together with the gates. Since the output amplitudes of outputs A and B may be approximately Vcc, they can be easily created using complementary MOS integrated circuits. FETQ2 and Q,2
A bias voltage is applied to the gate of.

This voltage is given by voltage dividing circuits R and R2 provided in common to a large number of gate circuits. Let G be the voltage dividing point of the voltage dividing circuit. The divided voltage is Vcc=5V~1
5V should be about 3V. Next, the operation of the embodiment shown in FIG. 3 will be explained, focusing on the differences from the conventional example shown in FIG.

FETQ repeats on and off according to the scale signal A.

In the off state, the source-drain resistance RD of FETQ
s is close to infinity and becomes a finite value RoN in the on state. FETQ gradually becomes R depending on the voltage of control signal Vs.
s changes. Therefore, FETQ has FETQ5
, Q3, Q, flow in a pulsed manner according to the scale signal frequency, and the same current flows out from the drain of FET Q6. Therefore, if the bias voltage is set so that a current that is half of the drain current of the FETQ flows through FETQ2, a second
A current with the same waveform as shown in the figure flows out. Thus, the embodiment of FIG. 3 uses FE
Using TQ and Q2, FETQ is turned on and off according to a scale signal, and the DC voltage required to eliminate the vedestal is applied to the gate of FETQ2.

Therefore, when the control signal Vs is OV and FETQ and Q are off, no current flows in both FETQ and Q2.
Therefore, there is no power consumption. Moreover, the voltage dividing circuit R,
and R2 can be provided in common for a large number of gate circuits, so their area and power consumption can be ignored. Note that the mirror gain of the current amplifier constituted by FETs Q5 and Q6 may be 1.

When the mirror gain is set to 1 in this way, FETQ5 and Q
Since the dimensions of 6 can be made the same, integrated circuit design becomes easier. In addition, the current output Vo obtained at each output terminal
, V, o are the operational amplifier 12 and the resistor Ro as shown in FIG.
, R, o, and Rf.

Vcc/2, which is half of the power supply voltage Vcc, may be applied to the positive input terminal of the operational amplifier 12. Further, even with the configuration as shown in FIG. 3, vedestal occurs if the duty ratio of the scale signal is not 50%.

This point is also pointed out in Tokoseki Publication No. 1376/1983. In Tokusekki No. 52-1376, it is stated that this vedestal can be removed by changing the mirror gain of the current amplifier from 2 to another value, but in reality, the mirror gain can be freely changed from the outside. This is difficult to change and requires changing the design of the current amplifier itself. However, in the embodiment shown in FIG. 3, the vedestal can be freely changed simply by changing the voltage at the voltage dividing point G from the outside. Therefore, even if the duty ratio of the scale signal applied to the gate circuit is not constant, it is possible to easily remove the vedestal signal. FIG. 5 shows another embodiment of the invention.

In FIG. 5, parts having the same functions as those in FIG. 3 are denoted by the same reference numerals, and the explanation thereof will be omitted, and the explanation will focus on the differences from FIG. 3. A T flip-flop 10 is installed at the gate of FETQ2.
The output A of is applied. The output B of the T flip-flop 11 is applied to the gate of FETQ,2. In this way, FETs Q and Q2 are turned on and off in opposite phases.

In this case, current is supplied from FETQ6 and FETQ
4 draws the current and alternately supplies and draws the current. Therefore, unlike the embodiment shown in FIG. 3, it is not necessary to apply a bias voltage, and the output current can be twice that of the embodiment shown in FIG. In this case, when making an integrated circuit,
It is advantageous that the voltage dividing circuits R and R2 of FIG. 3 are not provided. In the above explanation, a square wave was used as the scale signal voltage source, but a sine wave or a mirror tooth wave was used to connect the FETs Q,,Q, . ,Q
It may be applied to the gates of 2, Q, and 2.

In this case, the output waveform may be slightly distorted, but this is not a practical problem. Further, in the above description, a MOS field effect transistor was used, but the same effect can be obtained using a bipolar transistor. As mentioned above,
The present invention includes first to fourth active elements each having three terminals, and a current mirror circuit, wherein each first terminal of the first and second active elements is grounded, and each second terminal is grounded. are respectively connected to the first terminals of the third and fourth active elements, and the second terminals of the third and fourth active elements are respectively connected to the input terminal and the output terminal of the current mirror circuit, Applying a control signal for envelope control to each third terminal of the third and fourth active elements, and applying a scale signal to at least one of each third terminal of the first and second active elements, A bidirectional output current is taken out from the output terminal of the current mirror circuit.

In this way, the above-mentioned scale signal is transmitted between the capacitance between the 2t and 3rd terminals of the first active element and the first and third terminals of the third active element.
After being voltage-divided by the capacitance between the terminals, the voltage is supplied to the second terminal of the third active element via the capacitance between the first and second terminals of the third active element. and generally the first of the third active elements.
Since the capacitance between the second terminals is sufficiently d compared to the capacitance between the first and third terminals, a large voltage division ratio can be realized. As a result, according to the gate circuit of the present invention, the leakage of the scale signal can be made very small, and it is possible to reliably prevent the occurrence of a small "chee" sound even when no key is pressed. . Furthermore, while maintaining the effect of eliminating the pedestal of the conventional circuit, the area can be reduced when integrated into a circuit, and power consumption during standby can be virtually eliminated.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing the gate circuit of a conventional electronic musical instrument, Fig. 2 is its operating waveform diagram, Fig. 3 is a circuit diagram showing an embodiment of the present invention, and Fig. 4 is shown after Fig. 3. FIG. 5 is a circuit diagram showing a connected adder, and FIG. 5 is a circuit diagram showing another embodiment of the present invention. Q, ~Q4,Q,. ~Q, 4...n channel FET, Q, Q6, Q, 5, Q, 6...p channel F
ET, Vs, V, s... Control signal, Vo, V,
. ...Current output, V...Power supply, G...
...Voltage division point, E...Tamaji, 9...Input terminal, 10, 11...T flip-flop.
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Scope of Claims] 1. A device comprising first to fourth active elements each having three terminals, and a current mirror circuit, wherein the first terminals of the first and second active elements are grounded, and each of the first to fourth active elements has three terminals. A second terminal is connected to each first terminal of the third and fourth active elements, and a second terminal of each of the third and fourth active elements is connected to an input terminal and an output terminal of the current mirror circuit, respectively. connection,
A control signal for envelope control is applied to each of the third and fourth third terminals, a scale signal is applied to at least one of each of the third terminals of the first and second active elements, and the current mirror A gate circuit for an electronic musical instrument that extracts bidirectional output current from the output terminal of the circuit. 2 In the statement of claim 1, the first and second
A gate circuit for an electronic musical instrument, wherein a scale signal is applied to ten directions of each third terminal of an active element, and a bias voltage is applied to the other side. 3 In the description of claim 1, the first and second
A gate circuit for an electronic musical instrument, which applies scale signals having mutually opposite phases to each third terminal of an active element. 4 In the description of claim 1, the first to fourth
A plurality of sets including an active element and a current mirror circuit are provided, and a scale signal is applied to the third terminal of the first active element of each set, and the third terminal of the second active element of each set is applied. A gate circuit for electronic musical instruments that applies a common bias voltage to both. 5. In any one of claims 1 to 4, the first to fourth active elements and the current mirror circuit are incorporated into a complementary MOS integrated circuit. gate circuit for electronic musical instruments. 6. The gate of an electronic musical instrument as set forth in claim 2 or 4, wherein the bias voltage is changed according to the duty cycle of the scale signal so that the pedestal portion of the output current is always constant. circuit. 7. In any one of claims 1 to 6, the active element is constituted by a field effect transistor, and the first, second, and third terminals are respectively a source, a drain, and a gate. A gate circuit for an electronic musical instrument characterized by the following. 8. In any one of claims 1 to 6, the active element is constituted by a bipolar transistor, and the first, second, and third terminals are emitters,
A gate circuit for an electronic musical instrument characterized by a collector and a base.