JPS6031369B2 - Amplitude equalization circuit - Google Patents
Amplitude equalization circuitInfo
- Publication number
- JPS6031369B2 JPS6031369B2 JP2494679A JP2494679A JPS6031369B2 JP S6031369 B2 JPS6031369 B2 JP S6031369B2 JP 2494679 A JP2494679 A JP 2494679A JP 2494679 A JP2494679 A JP 2494679A JP S6031369 B2 JPS6031369 B2 JP S6031369B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- terminal
- amplitude
- frequency
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/04—Control of transmission; Equalising
- H04B3/14—Control of transmission; Equalising characterised by the equalising network used
- H04B3/143—Control of transmission; Equalising characterised by the equalising network used using amplitude-frequency equalisers
- H04B3/144—Control of transmission; Equalising characterised by the equalising network used using amplitude-frequency equalisers fixed equalizers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Waveguide Connection Structure (AREA)
- Filters And Equalizers (AREA)
Description
【発明の詳細な説明】
この発明は例えば無線通信において、フェージングによ
り生じる振幅歪を等化する場合に適する振幅等化回路に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an amplitude equalization circuit suitable for equalizing amplitude distortion caused by fading in, for example, wireless communication.
従来の振幅等化回路は第1図に示すように入力端子11
と、出力端子12との間に等化特性の尖鋭度を調整する
可変抵抗素子13が接続される。The conventional amplitude equalization circuit has an input terminal 11 as shown in FIG.
A variable resistance element 13 is connected between the output terminal 12 and the output terminal 12 for adjusting the sharpness of the equalization characteristic.
出力端子12及び共通端子、即ち接地との間にフェージ
ングの中心周波数の1/傘皮長の分布定数線路14が接
続されている。入力端子11及び共通端子間に低出力イ
ンピーダンスの信号源15が接続される。この従来の回
路は、フェージングの中心周波数の変化にそもなって線
路14の長さを変えなければならない。従って、実際の
振幅等化回路としては第2図に示すようにコイル16及
び可変コンデンサー7で構成される。A distributed constant line 14 of 1/the umbrella skin length of the center frequency of fading is connected between the output terminal 12 and a common terminal, that is, ground. A low output impedance signal source 15 is connected between the input terminal 11 and the common terminal. In this conventional circuit, the length of the line 14 must be changed as the fading center frequency changes. Therefore, an actual amplitude equalization circuit is composed of a coil 16 and a variable capacitor 7 as shown in FIG.
直列共振回路18が線路14と共通端子との間に直列に
挿入される。可変コンデンサ17の容量を変化させて共
振回路18の共振周波数を変えることにより線路14の
長さを等価的に変えていた。この第2図に示した従来の
回路においては、線路長可変幅を大きくするためには直
列共振回路18の共振周波数の変化を大きく、即ちコイ
ル16のィンダクタンス、コンデンサ17の静電容量の
変化幅を大きくしなければならない。A series resonant circuit 18 is inserted in series between the line 14 and the common terminal. By changing the capacitance of the variable capacitor 17 and changing the resonant frequency of the resonant circuit 18, the length of the line 14 is equivalently changed. In the conventional circuit shown in FIG. 2, in order to increase the line length variable range, the resonant frequency of the series resonant circuit 18 must be changed greatly, that is, the inductance of the coil 16 and the capacitance of the capacitor 17 must be changed. The width must be increased.
しかしVHF帯以上で使用可能な、電気的にィンダクタ
ンスを変化できる素子は入取し難く、前記共振周波数の
変化幅はコンデンサ17の静電容量の変化幅で決定され
る。このため線路長を等価的に大きく変化させることが
できないのが実情であった。つまり実際のフェージング
の中心周波数が広帯域に亘たり変動する場合にその振幅
歪を等化することはできない。このような点より分布定
数線路の入力端子及び出力端子の少なくも一方と共通端
子その間に可変容量素子を接続してその可容量素子の容
量値を変化せて振幅等化特性の中心周波数を変化させる
ことが提案されている。However, it is difficult to obtain an element that can electrically change the inductance and can be used above the VHF band, and the range of change in the resonant frequency is determined by the range of change in the capacitance of the capacitor 17. For this reason, the actual situation is that it is not possible to equivalently change the line length significantly. In other words, when the center frequency of actual fading varies over a wide band, the amplitude distortion cannot be equalized. From this point, a variable capacitance element is connected between at least one of the input terminal and output terminal of the distributed constant line and the common terminal, and the capacitance value of the capacitance element is changed to change the center frequency of the amplitude equalization characteristic. It is proposed that
例えば第3図に第1図と対応する部分に同一符号を付け
て示すように分布定数線路14の入力端子及び出力端子
と共通端子との間に可変容量素子として可変容量ダイオ
ード(パラクタダィオード)21及び22がそれぞれ接
続される。線路14の共通端子側は交流信号阻止用チョ
ークコイル23を通じて可変容量ダイオード制御用電圧
入力端子24に接続される。この例では可変抵抗素子1
3としてPmダイオードを用いた場合で、その両端に直
流阻止用コンデンサ25及び26がそれぞれ直列に挿入
される。そのコンデンサ及びPINダイオードの各接続
点は交流信号阻止用チョークコイル27及び28をそれ
ぞれ通じてPINダイート制御用電圧入力端子29及び
31に接続される。線路14及び可変容量ダイオード2
1の差続点と出力端子12との間に直列に直流阻止用コ
ンデンサ32が挿入される。この第3図に示した回路の
入出力間振幅特性日(■)は‘1}式のように示される
。こ)で、PINダイオード13の抵抗値をR、可変容
量ダイオード21,22の各静電容量をC、線路14の
特性インピーダンスをZo、その長さを1、位相定数を
8、かつ無損失であるとする。この特性日(山)は、P
INダイオード13の抵抗R、可変容量ダイオード21
,22の容量Cを変化するとそれぞれ第4図、第5図に
示すようになる。For example, as shown in FIG. 3 with the same reference numerals assigned to parts corresponding to those in FIG. ) 21 and 22 are connected, respectively. The common terminal side of the line 14 is connected to a voltage input terminal 24 for controlling a variable capacitance diode through a choke coil 23 for blocking an AC signal. In this example, variable resistance element 1
In this case, a Pm diode is used as the Pm diode, and DC blocking capacitors 25 and 26 are inserted in series at both ends of the Pm diode. Connection points between the capacitor and the PIN diode are connected to voltage input terminals 29 and 31 for controlling the PIN diode through AC signal blocking choke coils 27 and 28, respectively. Line 14 and variable capacitance diode 2
A DC blocking capacitor 32 is inserted in series between the connection point 1 and the output terminal 12. The input-output amplitude characteristic (■) of the circuit shown in FIG. 3 is expressed by the equation '1}. ), the resistance value of the PIN diode 13 is R, each capacitance of the variable capacitance diodes 21 and 22 is C, the characteristic impedance of the line 14 is Zo, its length is 1, the phase constant is 8, and there is no loss. Suppose there is. This characteristic day (mountain) is P
Resistance R of IN diode 13, variable capacitance diode 21
, 22 are changed as shown in FIGS. 4 and 5, respectively.
即ち端子29,31間に制御電圧を加えてPINダイオ
ード13の抵抗Rを変えることにより第4図に示すよう
にフェージング等化特性の尖鋭度を変化することができ
、また、端子24に制御電圧を加えて可変容量ダイオー
ド21,22の容量Cを変えることにより第5図から明
らかなよう※にフェージング等化特性の中心周波数を変
えることができる。一方、第2図に示した従釆の回路の
入出力間振幅特性H′(の)は‘2}式のように示され
る。That is, by applying a control voltage between the terminals 29 and 31 and changing the resistance R of the PIN diode 13, the sharpness of the fading equalization characteristic can be changed as shown in FIG. By adding C and changing the capacitance C of the variable capacitance diodes 21 and 22, the center frequency of the fading equalization characteristic can be changed as is clear from FIG. On the other hand, the input-output amplitude characteristic H' of the subordinate circuit shown in FIG. 2 is expressed by equation '2}.
こ)で可変抵抗素子13の抵抗値をR、直列共振回路1
8のコイル16及びコンデンサー7のインダクタンス及
び容量をそれぞれL,C、線路14の特性インピーダン
スはZo、長さを1、位相定数を8、かつ無損失である
とする。こ)で筆化特性の中心周波数は【1}及び■式
より次のように求まる。), the resistance value of the variable resistance element 13 is R, and the series resonant circuit 1 is
It is assumed that the inductance and capacitance of the coil 16 and capacitor 7 of 8 are L and C, respectively, the characteristic impedance of the line 14 is Zo, the length is 1, the phase constant is 8, and there is no loss. In this case, the center frequency of the writing characteristic can be found from [1} and equation (2) as follows.
第3図の回路の場合
乙・COS31−ゆZ2‐才)Sin81=o‘3,第
2図の回路の場合乙.C。In the case of the circuit shown in Fig. 3, B. C.
S81−(心−才)SinG1=o‘4)この両式を比
較することにより、第2図の回路のコイルのィンダクタ
ンスしは第3図の回路ではC・Zよと表わせられる。即
ち第3図の回路では容量Cを変えることにより等価的に
コイル16のィンダクタンスを変えることができる。こ
の結果第2図の回路に比して第3図の回路は中心周波数
を広帯域に変化できる。しかし、この第3図の回路の振
幅特性は第6図に示すように中心周波数foと零周波数
(直流)とのほぼ中間に反共振点が有り、この周波数近
傍においてはフェージングによる振幅特性を筆化するこ
とができない。S81-(shin-sai)SinG1=o'4) By comparing these two equations, the inductance of the coil in the circuit of FIG. 2 can be expressed as C.Z in the circuit of FIG. That is, in the circuit shown in FIG. 3, by changing the capacitance C, the inductance of the coil 16 can be equivalently changed. As a result, compared to the circuit of FIG. 2, the circuit of FIG. 3 can vary the center frequency over a wider range. However, as shown in Figure 6, the amplitude characteristics of the circuit shown in Figure 3 have an anti-resonance point approximately midway between the center frequency fo and the zero frequency (DC), and the amplitude characteristics due to fading occur near this frequency. cannot be converted into
即ち第6図において中心周波数らを中心に土△F2/2
の帯域は等化可能であるが前記反共振周波数と中心周波
数foとの周波数差より大きい周波数を△f,とすると
foを中心に土△F,/2の帯城に亘つて等化すること
はできない欠点がある。この発明の目的は広い周波数帯
にわたって中心周波数を変化することができ、しかも中
心周波数と零周波数(直流)との中間に生じる反共振点
を除去し、広い帯城にわたって等化できる振幅等化回路
を提供することにある。That is, in Fig. 6, △F2/2 is centered around the center frequency et al.
It is possible to equalize the band, but if △f is a frequency that is greater than the frequency difference between the anti-resonance frequency and the center frequency fo, equalization can be performed over a band of △F, /2 with fo as the center. There is a drawback that it cannot be done. The purpose of this invention is to provide an amplitude equalization circuit that can change the center frequency over a wide frequency band, eliminate the anti-resonance point that occurs between the center frequency and zero frequency (DC), and equalize over a wide frequency band. Our goal is to provide the following.
この発明によれば入力端子及び出力端子間に可変抵抗素
子が接続され、前記入力端子及び出力端子の一方と共振
端子との間に分布定数線路が設けられ、その分布定数線
路の入力端子及び出力端子の少くとも一方と共通端子と
の間に可変容量素子が接続され、その可変容量素子と並
列にィンダクタンス素子が接続される。。このィンダク
タンス素子のインピーダンスはその周囲の回路のインピ
ーダンス、即ち並列に接続された可変容量素子のインピ
ーダンスよりも十分大きく選定される。前記中心周波数
らより低い周波数において前記ィンダクタンス素子のイ
ンピーダンスが小さくなるため、入出力間の挿入損失が
大きくなり、前記反共振周波数が発生しない。例えば第
7図に第3図と対応する部分に同一符号を付けて示すよ
うに、この発明では可変容量ダイオード22と並列にイ
ンダクタンス素子としてコイル33が直流阻止用コンデ
ンサ34を介して接続される。According to this invention, a variable resistance element is connected between an input terminal and an output terminal, a distributed constant line is provided between one of the input terminal and output terminal and a resonant terminal, and the input terminal and the output of the distributed constant line are A variable capacitance element is connected between at least one of the terminals and the common terminal, and an inductance element is connected in parallel with the variable capacitance element. . The impedance of this inductance element is selected to be sufficiently larger than the impedance of the surrounding circuit, that is, the impedance of the variable capacitance element connected in parallel. Since the impedance of the inductance element becomes small at frequencies lower than the center frequency, insertion loss between input and output becomes large, and the anti-resonance frequency does not occur. For example, as shown in FIG. 7 with the same reference numerals assigned to parts corresponding to those in FIG. 3, in the present invention, a coil 33 is connected as an inductance element in parallel with the variable capacitance diode 22 via a DC blocking capacitor 34.
コイル33のィンダクタンス値L沖o周波数らの近く‘
こおし・て岬L>才肌ちコイル33のインピーダンスが
周囲の回路のインピーダンスに比べて十分大きくなるよ
うに選定される。このようにすると、この第7図に示し
た回路の入出力間の振幅特性はコイル33が無い場合の
入出力間振幅特性に等しくなる。一方、コイル33は零
周波数(直流)においてはインピーダンスが零となるた
め、霧周波数付近においてこの第7図の等化回路の入出
力間の挿入損失が大となるように働く。The inductance value of the coil 33 is near the frequency L
The impedance of the coil 33 is selected so as to be sufficiently large compared to the impedance of the surrounding circuit. In this way, the amplitude characteristic between the input and output of the circuit shown in FIG. 7 becomes equal to the amplitude characteristic between the input and output when the coil 33 is not provided. On the other hand, since the impedance of the coil 33 is zero at zero frequency (DC), the insertion loss between the input and output of the equalization circuit shown in FIG. 7 becomes large near the fog frequency.
この様子を第8図に示す。こ)で実線はコイル33が設
けられた場合、破線はコイル33が除去された場合に各
入出力間振幅特性である。このようにコイル33は中心
周波数fo付近の特性を変えずに中心周波数foと雫周
波数数との中間にあった反共振点を無くするように作用
する。その結果コイル33を付加したこの発明の等化回
路は中心周波数foを中心に広い周波数範囲に亘つてフ
ェージングを等化できる。しかも可変容量素子21,2
2の容量値を変化することにより中心周波数foを前述
したように広い周波数範囲にわたって変化させることが
できる。第7図の回路と相対関係にある第9図の回路、
即ち分布定数線路14を入力端子11側に接続しても以
上説明したと同機の効果が得られることは明らかである
。第7図、第9図に示した一実例において可変容量ダイ
オード21,22の容量及びその変化を等しくせず、異
った特性のものを用いても上記の効果はそこなわれない
。更に可変容量ダイオード21と並列にインダクタンス
素子33を接続してもよい。また可変容量ダイオード2
1,22の両者にそれぞれ各別ィンダクタンス素子を接
続してもよい。また分布定数線路14の入力側及び出力
側の一方の可変容量子を省略してもよい。This situation is shown in FIG. In this case, the solid line is the amplitude characteristic between each input and output when the coil 33 is provided, and the broken line is the amplitude characteristic when the coil 33 is removed. In this way, the coil 33 acts to eliminate the anti-resonance point located between the center frequency fo and the droplet frequency without changing the characteristics near the center frequency fo. As a result, the equalization circuit of the present invention including the coil 33 can equalize fading over a wide frequency range around the center frequency fo. Moreover, the variable capacitance elements 21, 2
By changing the capacitance value of 2, the center frequency fo can be changed over a wide frequency range as described above. The circuit of FIG. 9, which is relative to the circuit of FIG. 7,
That is, it is clear that the same effect as described above can be obtained even if the distributed constant line 14 is connected to the input terminal 11 side. In the example shown in FIGS. 7 and 9, the above effect is not impaired even if the variable capacitance diodes 21 and 22 are not made equal in capacitance and change in capacitance and are used with different characteristics. Furthermore, an inductance element 33 may be connected in parallel with the variable capacitance diode 21. Also, variable capacitance diode 2
Separate inductance elements may be connected to both 1 and 22, respectively. Further, the variable capacitor on either the input side or the output side of the distributed constant line 14 may be omitted.
第1図は従来の振幅等化回路の原理図、第2図は従来の
振幅等化回路を示す回路図、第3図は提案されている振
幅等化回路の一例を示す回路図、第4図は第3図の回路
において可変抵抗素子13の抵抗値Rを変化させた時の
入出力振幅特性の変化状態を示す曲線図、第5図は第3
図の回路において可変容量ダイオードの容量値を変化さ
せた時の入出力振幅特性の変化状態を示す曲線図、第6
図は第3図の回路の入出力特性曲線図、第7図はこの発
明による振幅等化回路の一例を示す回路図、第8図は第
7図の回路の入出力振幅特性を示す曲線図、第9図は第
7図に示した回路と相対関係にある回路例を示す回路図
である。
11・・・・・・入力端子、12・・・・・・出力端子
、13…・・・可変抵抗素子、14・・・・・・分布定
数線路、15・・・・・・信号線、21,22・・・・
・・可変容量素子、23,27,28・・・・・・信号
阻止用チョークコイル、24・・・・・・可変容量ダイ
オード制御用電圧入力端子、29,31・・・・・・P
INダイオード制御用電圧入力端子、25,26,32
〜34・・・・・・直流阻止用コンデンサ。
第1図
第2図
第3図
第4図
第5図
第6図
第7図
第8図
第9図Fig. 1 is a principle diagram of a conventional amplitude equalization circuit, Fig. 2 is a circuit diagram showing a conventional amplitude equalization circuit, Fig. 3 is a circuit diagram showing an example of a proposed amplitude equalization circuit, and Fig. 4 is a circuit diagram showing an example of a proposed amplitude equalization circuit. The figure is a curve diagram showing how the input/output amplitude characteristics change when the resistance value R of the variable resistance element 13 is changed in the circuit of Figure 3.
Curve diagram 6 showing how the input/output amplitude characteristics change when the capacitance value of the variable capacitance diode is changed in the circuit shown in the figure.
The figure is an input/output characteristic curve diagram of the circuit in Figure 3, Figure 7 is a circuit diagram showing an example of an amplitude equalization circuit according to the present invention, and Figure 8 is a curve diagram showing input/output amplitude characteristics of the circuit in Figure 7. , FIG. 9 is a circuit diagram showing an example of a circuit that is in a relative relationship with the circuit shown in FIG. 11... Input terminal, 12... Output terminal, 13... Variable resistance element, 14... Distributed constant line, 15... Signal line, 21, 22...
...Variable capacitance element, 23, 27, 28...Choke coil for signal blocking, 24...Variable capacitance diode control voltage input terminal, 29,31...P
IN diode control voltage input terminal, 25, 26, 32
~34...DC blocking capacitor. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9
Claims (1)
振幅等化特性を有する振幅等化回路において、 前記出
力端子及び前記出力端子間に接続された可変抵抗素子と
、 前記出力端子と前記共通端子との間あるいは前記出
力端子と共通端子との間に設けられた分布定数線路と、
その分布定数線路の入力端子及び出力端子の少なくと
も一方と前記共通端子との間に接続された可変容量素子
と、 その可変容量素子と並列に接続され、等化すべき
信号の中心周波数近傍で前記可変容量素子のインピーダ
ンスよりも大きいインピーダンスをもつインダクタンス
素子とを具備する振幅等化回路。1. In an amplitude equalization circuit having an input terminal, an output terminal, and a common terminal, and having a certain amplitude equalization characteristic, the variable resistance element connected between the output terminal and the output terminal; a distributed constant line provided between the terminal or between the output terminal and the common terminal;
a variable capacitance element connected between at least one of the input terminal and output terminal of the distributed constant line and the common terminal; An amplitude equalization circuit comprising an inductance element having an impedance larger than the impedance of the capacitance element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2494679A JPS6031369B2 (en) | 1979-03-02 | 1979-03-02 | Amplitude equalization circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2494679A JPS6031369B2 (en) | 1979-03-02 | 1979-03-02 | Amplitude equalization circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55117320A JPS55117320A (en) | 1980-09-09 |
| JPS6031369B2 true JPS6031369B2 (en) | 1985-07-22 |
Family
ID=12152172
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2494679A Expired JPS6031369B2 (en) | 1979-03-02 | 1979-03-02 | Amplitude equalization circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6031369B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4697481B2 (en) * | 2008-01-21 | 2011-06-08 | 三菱電機株式会社 | Amplitude equalizer |
-
1979
- 1979-03-02 JP JP2494679A patent/JPS6031369B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55117320A (en) | 1980-09-09 |
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