JPS603201B2 - Erroneous control prevention device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control prevention device that prevents a controlled object from being controlled inadvertently when an output signal from a control device is erroneous for some reason.

FIG. 1 is a block diagram showing an example of a conventional yield control prevention device.
...11mn are each controlled target equipment, 2 is a control device for the purpose of centralized control of multiple controlled target equipment, 3
-1,...31m correspond to the control target equipment 1-11,...11ml according to the output signal of the control device 2, respectively.
, etc. Control output circuit for driving 4-11
,4-12,...4-ln;41ml,...
・4-mn is each controlled device 1-11, 1-1
Interlock circuits provided corresponding to 2,...1-ln; 1-ml,...1-mn, 5-1,...5m are control output circuits 3-17... . . 31m is a gate circuit that selectively blocks the output signal to m, and 6 is a gate operation unit that controls the state of the gate circuit 5-1.

Furthermore, each controlled device has two states, a first state (for example, "on" state) and a second state (for example, "off" state), and is changed from the first state to the second state by the first signal. The second state is switched to the first state by the second signal. Further, each ink lock circuit has two states, a locked state and an unlocked state, and is switched from the locked state to the unlocked state by a third signal,
The unlocked state is switched to the locked state by the fourth signal, and each gate circuit has two states, a first mode and a second mode, and the gate operating section switches between these two modes. selected. Furthermore, as shown in FIG. 1, one control device 2 includes multiple sets of gate circuits 5-1,...
....5-m is connected, and one set of gate circuits, for example, one set of control output circuits 3-1 corresponding to gate circuits 5-1.
are connected, and a plurality of interlock circuits 4-11, 4-12, . . . 4- are connected to one set of control output circuit 3-1.
The corresponding controlled devices 1-11,
1-12, . . . 1-ln are connected.

Furthermore, in a normal case, the first signal is not present, and the fourth signal is coded and added with a necessary address signal and transmitted in a time-division manner over a single transmission line, but for convenience of explanation, in FIG. 1,...7-m is the transmission line for the first signal and the second signal, and 8-1,...8-m is the transmission line for the third signal and the fourth signal. and transmission line. In the circuit shown in FIG. 1, all the controlled devices and all the interlock circuits operate in the same way, so in the following explanation, the controlled devices 1-11 and the interlock circuits 4-11 will be described as examples.

9-11 and 10-11 are the controlled devices 1-1, respectively.
1. Interlock circuit 4-1 This is a signal transmission line for notifying the control device 2 of the state of interlock circuit 4-1.

In the conventional device, when the interlock circuit 4-1 is in the locked state, it blocks the second signal, but when it is in the unlocked state, both the first signal and the second signal are passed through and the interlock circuit 4-1 is controlled. Input to device 1-11, gate circuit 5
-1 passes through all of the first signal, second signal, third signal, and fourth signal when it is in the first mode, inputs it to the control output circuit 3-1, and inputs the second signal to the control output circuit 3-1. is connected to block the third signal when in mode. Therefore, in order to bring the controlled equipment 1-11 into the second state and reliably maintain this state, an interlock circuit 4-11 is required. It is sufficient to make the gate circuit 5-1 vertically in the shape of a cross and to set the gate circuit 5-1 to the second mode. If this is done, even if a malfunction occurs in the control device 2, the third signal for setting the interlock circuit 4-11 to the unlocked state will be blocked by the gate circuit 5-1. does not enter the first state, ensuring failsafe. Note that arbitrary control is possible for devices to be controlled that do not have an interlock device or whose corresponding interlock device is in an unlocked state.

For example, if the interlock circuit 4-12 is in the unlocked state, the first signal and the second signal are connected to the gate circuit 5-1.
, and also passes through the interlock circuit 4-12, so the states of the controlled devices 1-12 can be switched freely.
Since the subordinate device is configured as described above, there are a plurality of devices that are held in the second state, and for example, the controlled devices 1-11 and 1-12 are held in the second state. some of them, for example, controlled equipment 1-12.
The interlock circuit 4-12 must be unlocked in order to put the interlock circuit 4-11 in the first state. Transferring the signal to transmission line 8-1
When the interlock circuit 4-11 is output to the transmission line 7-1, the interlock circuit 4-11 becomes unlocked. Next, when the control device 2 mistakenly outputs the second signal for the controlled device 1-11 to the transmission line 7-1,
This signal passes through the interlock circuit 4-11 and intentionally controls the controlled equipment 1-11, so fail-safe is not guaranteed at this time.

This point is a drawback of the conventional device, and it is an object of the present invention to eliminate this drawback.Examples of the present invention will be described below with reference to the drawings. In order to most easily achieve the object of this invention, the gate circuit 5 in the circuit of FIG.
All you have to do is change the internal connections in item 1.

That is, the internal connections of the gate circuit 5 are such that the second signal is blocked when the gate circuit 5-1 is in the first mode, and the third signal is blocked when the gate circuit 5 is in the second mode. If you change the gate circuits 5-1, the third signal and the second signal will not pass through, regardless of which state the gate circuits 5-1 are in. Then ``
Controlled device 1 locked in “off” state)
is not intentionally controlled to become the first state (the "on" state in the above example). When controlling the controlled device 1-11 to the first state, the gate circuit 5-1 is put into the first state and the third signal is input from the control device 2 to the interlock circuits 4-11 to activate the interlock. After the circuit 4-11 is in the unlocked state, the gate operation unit 6 is operated to put the gate circuit 5-1 into the second mode, and the second
The signal is sent to the controlled device 1 via the interlock circuit 4-11.
All you have to do is enter it in 11.

In the present invention, a second gate circuit is further provided to ensure failsafe.

FIG. 2 is a block diagram showing an embodiment of the present invention, in which the control target equipment 1-11 and the control output circuit 3-1 shown in FIG. 1. Interlock circuit 4-11, transmission line 7-1, 8-1, 9-1, 10
-1, and other controlled devices, other control output circuits, other interlock circuits, and other transmission lines are omitted for convenience. Reference numeral 51 denotes a first gate circuit which is internally connected to block the second signal in the first mode and block the third signal in the second mode.

52 is a second gate circuit which is cascade-connected to the gate circuit 51 and has two types of states: a first mode and a second mode;
In the first mode, all the first, second, third, and fourth signals are passed; in the second mode, the first, second, third, and fourth signals are passed;
block all signals.

61 is a gate operating section for the gate circuit 51, and 62 is a gate operating section for the gate circuit 62. The state of the gate circuit 51 is controlled only from the gate operating section 61, and the gate circuit 52 changes from the first mode to the second mode. Switching to the mode can be performed by either a signal from the gate operating section 62 or the control device 2, and switching from the second mode to the first mode is controlled only from the gate operating section 62.

Further, 81 is a transmission line for transmitting a signal for controlling the gate circuit 52, and 11 is a transmission line for transmitting a signal for controlling the gate operation section 61 depending on the state of the gate circuit 52. Third
The figure is a time chart showing an example of the operation of the circuit shown in Figure 2, where the axis is time and the vertical axis is the state of the circuit, signal,
and operations are shown.

The operation of the circuit shown in FIG. 2 will be explained below with reference to FIG.

All of the controlled devices controlled by the control device 2 are
state, and the interlock circuit corresponding to each controlled device is in a locked state, locking the controlled device in the second state, switches the specific controlled device 1 to the first state. This will be explained using switching control as an example.
Since the gate circuit 51 is normally in the second mode and blocks passage of the third signal, the state of the gate circuit 51 is changed to the first mode by operating the gate operation section 61 during the above-mentioned switching control.
The mode is changed (t, time point). After this, control device 2
If the third signal is output at the time based on the judgment result of (
Since the gate circuit 52 is in the first mode), this signal is input to the interlock circuit 4 and the interlock circuit 4 becomes unlocked. Next, at time t3, the control device 2 puts the gate circuit 52 into the second mode and displays which interlock circuits remain locked. The operator of this device uses this display to confirm that there is no error in the interlock circuit that should remain locked (t4).
At the subsequent point T, the gate circuit 51 is put into the second mode, and then the gate circuit 52 is put back into the first mode. After that, the control device 2 outputs the second signal at the moment,
This signal passes through the gate circuits 51, 52 and the lock circuit 4, and switches the controlled device 1 to the first state. ``In the process of the operation shown in Figure 3, if the control straight line 2 sends a signal to the controlled device that should remain in the second state (in the example above, the R-off state) to switch to the first state. We prove that it is possible to reliably prevent malicious control even if .

In other words, the third signal (interlock release signal) and second signal (for example, input control signal) are output by mistake when the gate circuit is in the time period T1 (t, to t3) in Figure 3. Even so, the interlock circuit is erroneously unlocked by the third signal, and this intentional control is discovered by checking the state of the interlock at the time of the interlock, and does not result in yielding control of the device to be controlled.

Any signal is blocked by the gate circuit 52 during time period T2. Even if an erroneous signal is output in time period T3, the third signal does not pass through the gate circuit 51 and the interlock circuit is not unlocked, so the device to be controlled will not be controlled. In the above-mentioned embodiment, the second state of the controlled device 1 is locked by the interlock circuit 4, but it should be noted that either the "off" or "on" state of the controlled device 1 may be used as the second state. Not even.

As described above, according to the present invention, there is provided an erroneous control prevention device that does not intentionally control other controlled devices when controlling only a part of a plurality of interlocked controlled devices. Obtainable.

Figure 1 is a block diagram showing an example of a subordinate device, Figure 2 is a block diagram showing an embodiment of the present invention, and Figure 3 shows the operation of the circuit shown in Figure 2. It is a time chart showing an example.

In the figure, 1 is a device to be controlled, 2 is a control device, 3 is a control output circuit, 4 is an interlock circuit, 5, 51, and 52 are gate circuits, and 6, 61, and 62 are gate operation units, respectively. Note that the same reference numerals in each figure indicate the same or equivalent parts. Stem 3 diagram etc. - Diagram 2

Claims (1)

[Claims] 1. A controlled device that is switched from a first state to a second state by a first signal and switched from the second state to the first state by the second signal; The device is switched from the locked state to the unlocked state by a signal, and switched from the unlocked state to the locked state by a fourth signal, and inputs the first signal and the second signal. an interlock circuit which inputs the first signal and the second signal to the controlled device when only the control device is in the unlocked state; signal, the second signal, the third signal, and the fourth signal.
a gate circuit that inputs a signal, blocks the second signal in the first mode, blocks the third signal in the second mode, and passes other input signals and inputs them to the interlock circuit. An error control prevention device characterized by being equipped with. 2 A device to be controlled that is switched from a first state to a second state by a first signal and switched from the second state to the first state by a second signal, and is switched from a locked state to a locked state by a third signal. When the lock is switched to the unlocked state and the lock is switched from the unlocked state to the locked state by a fourth signal, the first signal and the second signal are input, and in the locked state, only the first signal is switched to the unlocked state. is an interlock circuit that inputs the first signal and the second signal to the device to be controlled; signal, the third signal, and the fourth signal.
A first signal is input to the interlock circuit, the second signal is blocked in the first mode, the third signal is blocked in the second mode, and the other input signals are passed through and input to the interlock circuit. a gate circuit connected in cascade to the first gate circuit and inputting the first signal, the second signal, the third signal, and the fourth signal to block all input signals; An erroneous control prevention device comprising a second gate circuit that is controlled to either pass or pass.