JPS603223B2 - Central processing unit error collection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error collection method for a central processing unit that automatically collects the internal state of the central processing unit where the error occurred when an error occurs in the central processing unit. .

In the prior art, when an error occurs in the central processing unit, the central processing unit is brought into a clock-stop state and its internal state is written to a predetermined area of the main memory.

This error collection method requires a logout mechanism or collection mechanism for each central processing unit when multiple central processing units are present in the system, and a logout mechanism or collection mechanism must be provided for each central processing unit. If another central processing unit cannot use the main memory, a sufficient logout area cannot be secured in the main memory, or a failure occurs in the bus between the central processing unit and the main memory. has drawbacks such as the inability to perform log-awaiting. The present invention aims to provide a central processing unit error collection scheme that does not have the above-mentioned drawbacks.

Therefore, the central processing unit error collection method of the present invention includes a plurality of central processing units, a service processor that manages and maintains the system, a system console interface mechanism, and the plurality of central processing units described above. and a dedicated bus provided between the system console interface mechanism and the service processor, and a dedicated bus provided between the system console interface mechanism and the service processor; When an error occurs, the device notifies the system console interface mechanism of the error occurrence via a dedicated bus, stops its own clock, and receives a scanout completion notification from the system console interface mechanism. The system console interface mechanism is configured to resume processing;
When the error occurrence is notified, it scans out the status information of all predetermined logout points in the error occurrence central processing unit via a dedicated bus and stores it in its own memory, and then finishes the scanout. configured to notify the error occurrence central processing unit and the service processor via a dedicated bus,
After the service processor is notified of the completion of the scanout, the service processor connects the system to the system via a dedicated bus.
The present invention is characterized in that it is configured to retrieve the contents of the memory of the console interface mechanism and perform error analysis processing. Hereinafter, the present invention will be explained with reference to the drawings. FIG. 1 is a diagram of one embodiment of the present invention.

FIG. 2 is a diagram explaining the operation of the system of FIG. 1. In FIG. 1, 1 is a central processing unit, 2 is a system console interface mechanism, 3 is a service processor, 4 is a latch, 5 is an AND gate, 6 is a memory, and 7 is an address register.

The memory within the interface mechanism 2 has a storage capacity capable of accommodating latch information of all latches 4 within the central processing unit 1. Address register 7 outputs a latch selection address and a write address for memory 6. Depending on the latch selection address, A
ND gate 5 opens and the latch information of latch 4 is sent to the latch information interface mechanism. The sent latch information is stored in the specified storage location. System console
The interface mechanism 2 is completely independent from the central processing unit and has an internal control circuit (not shown). Next, the operation shown in FIG. 1 will be explained.

When an error occurs in the central processing unit 1, the central processing unit 1
notifies the interface mechanism 2 of the occurrence of an error, and also stops its own clock. Address register 7 in interface mechanism 2 delivers the write address to memory 6 and the latch selection address. The latch selection address causes, for example, one byte of latch information to be transmitted to the interface mechanism 2 and written to the specified storage location in the memory 6. Each time latch information is sent, the memory address and latch selection address are incremented by one. When the latch information of all the latches in the central processing unit 1 has been written, the interface mechanism 2 notifies the central processing unit 1 that writing, that is, saving the latch information has been completed. When the central processing unit 1 receives the notification 2, it starts retrying. If the retry is successful, the process continues; if the retry is unsuccessful, the CPU is shut down. Success or failure of the retry is notified to the interface mechanism 2. The interface mechanism 2 notifies the service processor 3 that latch information has been written. The service processor 3 has an error analysis function, and upon receiving the above notification, it extracts the contents of the memory 6 and performs an error analysis process. As is clear from the above description, the present invention has the following advantages.

■ By simply installing one system console interface mechanism for multiple central processing units, it becomes possible to log out from each central processing unit.

In the conventional system, a logout mechanism was provided for each central processing unit. ■ Less hardware is required because the scanout bus is shared.

The scanout bus described above is conventional. ■ Since latch information is not written to main memory,
There is no need to stop other units or the central processing unit.

■ After writing the latch information to memory, the service processor is free to perform error analysis at any time.

■ Without using the data storage bus of the unit where the error occurred,
Since an independent bus is used, latch information can be collected reliably.

It also simplifies the design of the central processing unit. ■ Since latch information is not stored in the main memory, error collection can be performed without being affected by the layout of the main memory.

In the above description, the logout point is a latch, but it goes without saying that the gate output can be selected as the logout point.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of its operation. 1. ．． - Central processing unit, 2... System console interface mechanism, 3... Service processor, 4... Latch, 5... AND gate, 6.・．．
Memory, 7...address register. Spear 1 Diagram

Claims (1)

[Claims] 1 a plurality of central processing units, a service processor that manages and maintains the system, a system console interface mechanism, and a system installed between the plurality of central processing units and the system console interface mechanism; dedicated bus and the system console mentioned above.
A dedicated bus is provided between the interface mechanism and the service processor, and when an error occurs, each central processing unit communicates the error occurrence to the system console interface via the dedicated bus. Notify the system, stop its own clock, and restart the above system.
configured to resume processing upon receiving a notification of completion of scanout from the console interface mechanism;
When the system console interface mechanism is notified of the occurrence of an error, it scans out the status information of all predetermined logout points in the central processing unit where the error occurred via a dedicated bus and stores it in its own memory. and then notifies the error occurrence central processing unit and the service processor of the completion of the scanout via a dedicated bus, and the service processor is notified of the completion of the scanout. and thereafter, the contents of the memory of the system console interface mechanism are read out via a dedicated bus to perform error analysis processing.