JPS6032335A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6032335A JPS6032335A JP58141676A JP14167683A JPS6032335A JP S6032335 A JPS6032335 A JP S6032335A JP 58141676 A JP58141676 A JP 58141676A JP 14167683 A JP14167683 A JP 14167683A JP S6032335 A JPS6032335 A JP S6032335A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- pad
- wire
- bonding
- semiconductor device
- Prior art date
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07511—Treating the bonding area before connecting, e.g. by applying flux or cleaning
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/29—Bond pads specially adapted therefor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5434—Dispositions of bond wires the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5453—Dispositions of bond wires connecting between multiple bond pads on a chip, e.g. daisy chain
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
- H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/921—Structures or relative sizes of bond pads
- H10W72/923—Bond pads having multiple stacked layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/934—Cross-sectional shape, i.e. in side view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
- H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は、半導体装置、特に突起電極を有する半導体装
置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a protruding electrode.
従来、集積回路などの半導体装置において、最も一般的
に用いられてきた装置の端子と外部リードとの接続方法
は、ワイヤボンディング法である。Conventionally, in semiconductor devices such as integrated circuits, the most commonly used method for connecting device terminals and external leads is a wire bonding method.
かかる方法を用いるとき、そこで用いられる半導体装置
は通常以下の如き構造を持ってる。すなわち、半導体基
板表面は内部に含まれる素子の接続用開孔を除いて、5
i01 、 Si3N4などの絶縁被膜で覆われ、接続
用開孔は内部配線用金属によって結線され、必要な電気
的接続を与えられている。When such a method is used, the semiconductor device used therein usually has the following structure. In other words, the surface of the semiconductor substrate has a diameter of 5.
It is covered with an insulating film such as i01, Si3N4, etc., and the connecting holes are connected by internal wiring metal to provide the necessary electrical connections.
かくの如き内部配線の終端部、すなわち、外部リードと
の接続端は通常パッドと呼ばれ、半導体基板上の周辺部
に配置されている。これらの内部配線及びパッドの材料
には導電性、シリコンとのオーミック性、加工性などの
点から通常A7が用いられ、この内部配線表面は表面保
藤の目的で絶縁物によって核種されている。そして、熱
圧着法。The terminal end of such internal wiring, that is, the connection end with the external lead is usually called a pad, and is arranged at the periphery of the semiconductor substrate. A7 is usually used as the material for these internal wirings and pads from the viewpoints of conductivity, ohmic properties with silicon, workability, etc., and the surface of these internal wirings is nuclided with an insulator for the purpose of surface bonding. And then there's the thermocompression bonding method.
超音波圧着法などにより、外部リードがパッドに接続さ
れる。External leads are connected to the pads by ultrasonic crimping or the like.
他方、近年新たに注目を浴びているワイヤレスポンディ
ングにおいては、外部接続用端子として、金属突起(バ
ンプ)からなる突起電極を用意し、複数個の金属外部リ
ードとの接続を同時に実現するというのが特徴である。On the other hand, in wireless bonding, which has recently been attracting attention, protruding electrodes made of metal protrusions (bumps) are prepared as external connection terminals, and connections with multiple metal external leads can be realized simultaneously. It is characterized by
かかる金属バンプは、通常前記ワイヤーボンディング用
の通常構造のパッド部上に、T i −P t−Au
、 Cr−Cu−Auなどの金属構成を持って実現され
る。ここでTi。Such a metal bump is usually formed on the pad portion of the normal structure for wire bonding.
, Cr-Cu-Au. Ti here.
Crは、バンプと表面被覆絶縁膜(Si02,5i3N
4)との密着性が保証されること、Auは電気メッキに
よって容易に突起構造が実現でき、化学的に安定な金属
であること、PL、Cuは配線金属であるAlと突起金
属であるAuとの直接接触によるパープルプレーグやホ
ワイトプレーグ等の悪性の金属間化合物の出現を避けぜ
しめるために用いられている。Cr is applied to bumps and surface coating insulating film (Si02,5i3N
4) Au is a chemically stable metal that can easily form a protrusion structure by electroplating, and PL and Cu are bonded between Al, which is the wiring metal, and Au, which is the protrusion metal. It is used to avoid the appearance of malignant intermetallic compounds such as purple plague and white plague due to direct contact with.
第1図は、かかる従来のワイヤレスボンディング用半導
体装置の突起電極の構造を示す断面図である。FIG. 1 is a sectional view showing the structure of a protruding electrode of such a conventional wireless bonding semiconductor device.
シリコンなどの半導体基板1は5iOzなどの絶縁被膜
2で覆われ、この絶縁被膜2上にAlバッド3が設けら
れ、このAlパッド3上面にS i02 。A semiconductor substrate 1 made of silicon or the like is covered with an insulating film 2 of 5iOz or the like, an Al pad 3 is provided on this insulating film 2, and Si02 is deposited on the upper surface of this Al pad 3.
Si3N4などの表面保護膜4と、Ti、Orなどの密
着強化用金属と、Pt、Cuなどの障壁用金属とからな
る導電体5と、上部金属としてAuからなる金属バンプ
6が形成されている。なお、金属バンプ6は通常電気メ
ツキ法により形成される。A conductor 5 made of a surface protection film 4 such as Si3N4, a metal for reinforcing adhesion such as Ti or Or, and a barrier metal such as Pt or Cu, and a metal bump 6 made of Au as an upper metal are formed. . Note that the metal bumps 6 are usually formed by electroplating.
かかる構造の半導体装置にワイヤレスボンディングをほ
どこす際には、ます金属バンプ6に接続されるべき外部
リード7をこの金属バンプ6に接触させ、しかる後、約
450℃の高熱と1〜2.5kg/cm2の高圧力とを
約1秒間、この接触部上面に加えて、ボンディングが完
了する。When performing wireless bonding on a semiconductor device having such a structure, the external lead 7 to be connected to the metal bump 6 is brought into contact with the metal bump 6, and then exposed to high heat of approximately 450°C and 1 to 2.5 kg of heat. A high pressure of /cm2 is applied to the top surface of the contact for about 1 second to complete the bonding.
しかるに従来構造の金属バンプ6においては、上述のよ
うに、ボンディング時に高圧力が加えられることにより
、金属バンプ6直下の峠等電(+5にクラックが生じ、
その結果バンプ金属であるAuとパッド部配線金属であ
るAlが直接接触し、機械的低強度のパープルプレーグ
や、電気的高抵抗のホワイトプレーグができたり、又圧
力と同時に加えられる高熱により金楕バンプ6を形成す
る金属Auと、表面保護膜(Si02.5i3N4)
4との著しい熱膨張係数との差に基き、金属バッド6周
辺の表面保護膜4にクラックが生じ保賎効果を損うとい
う重大な信頼性上の欠点がある。However, in the metal bump 6 of the conventional structure, as mentioned above, due to high pressure being applied during bonding, cracks occur in the pass isoelectric (+5) directly under the metal bump 6,
As a result, the bump metal (Au) and the pad wiring metal (Al) come into direct contact, resulting in the formation of purple plague with low mechanical strength and white plague with high electrical resistance. Metal Au forming bump 6 and surface protective film (Si02.5i3N4)
Due to the significant difference in thermal expansion coefficient between the metal pad 6 and the metal pad 6, cracks occur in the surface protection film 4 around the metal pad 6, impairing the bonding effect, which is a serious drawback in terms of reliability.
上記の欠点を補うためにはAlバッド3から金属バンプ
6を離して形成させればよいが、そのためにはAl配線
用パターンの設計変更が必要になり必然的に、半導体装
置のコストアップに連なるためその実現は困難である。In order to compensate for the above drawbacks, it is possible to form the metal bumps 6 at a distance from the Al pads 3, but this requires a change in the design of the Al wiring pattern, which inevitably leads to an increase in the cost of the semiconductor device. Therefore, it is difficult to realize this goal.
本発明の目的は、上記の欠点を除去することにより、ボ
ンデング時に発生するパープルプレーグ。The object of the present invention is to eliminate the above-mentioned drawbacks, thereby eliminating the purple plaque generated during bonding.
ホワイトプレーグ及び表面保護膜のクラックなどの発生
を防止した高信頼性で、かつ簡単に形成できる構造の突
起電極を有する半導体装置を提供することにある。It is an object of the present invention to provide a semiconductor device having a protruding electrode having a structure that is highly reliable and can be easily formed, preventing the occurrence of cracks in white plaque and a surface protective film.
以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
第2図は本発明の一実施例の要部を示す断面図である。FIG. 2 is a sectional view showing essential parts of an embodiment of the present invention.
本実施例は、シリコンなどの半導体基板11とその上に
形成されたS i02などの絶縁膜12と、絶縁被膜1
2上に形成されたAlパッド13とAlバッド13の上
面の1部及び絶縁被膜12上に形成された5i02 、
8i3N4などからなる表面保護膜14と、Ti、Cr
などからなるAlパット13の上面に形成された密着強
化用金属と、pt。In this embodiment, a semiconductor substrate 11 made of silicon or the like, an insulating film 12 made of Si02 or the like formed thereon, and an insulating coating 1
5i02 formed on a part of the upper surface of the Al pad 13 and the insulating coating 12,
A surface protective film 14 made of 8i3N4 etc., Ti, Cr
A metal for reinforcing adhesion formed on the upper surface of the Al pad 13 made of PT.
Cuなどからなる障壁用金属とからなる導電体15と、
ワイヤボンデング法として熱圧着結合法により接続され
たAu1J−ド線の一部分からなる金属バンプ16とか
ら構成される。A conductor 15 made of a barrier metal made of Cu or the like;
It is composed of a metal bump 16 made of a part of an Au1J-coated wire connected by a thermocompression bonding method as a wire bonding method.
すなわち、本実施例が、第1図に示した従来例と異なる
点は、金属バンプを従来の電気メツキ法ではなく、ワイ
ヤボンデング法を用いて形成した点にある。本実施例の
金属バンプ16は、熱圧着法により接続されたAu1J
−ドを4電体J5上の部分を残して、それ以外は切9増
ったものであり、現在の自動化されたワイヤボンデング
装置により容易に形成することができる。しかもボンデ
ングは約300℃の温度と約Q、 5 kg/cm2の
圧力の低温、低圧力のもとて約03秒の短時間で行われ
るので、ボンデング時に、導電体15や保護膜14には
クラック発生などの悪影響を及はすことなく、電気的2
機械的に安定な金桃バンプが得られる。That is, this embodiment differs from the conventional example shown in FIG. 1 in that the metal bumps are formed using a wire bonding method instead of the conventional electroplating method. The metal bumps 16 of this embodiment are Au1J connected by thermocompression bonding.
The wire bonding section is made by cutting off the wire except for the part on the four-wire conductor J5, and can be easily formed using current automated wire bonding equipment. Furthermore, bonding is carried out in a short time of about 3 seconds at a temperature of about 300°C and a pressure of about 5 kg/cm2, so that the conductor 15 and protective film 14 are Electrical 2
A mechanically stable gold peach bump can be obtained.
さらに、かくして形成された金属バンプ16は、第2図
に示すように、その上部がボンデング用電極の圧接によ
り凹部が形成される。そこでこの金員バンプ16に接続
さるべき外部リード線17の先端の形状をあらかじめこ
の凹部の形に合せて折り曲げでおくか、又はリード劇料
としてボンデング時の圧力で容易にMl)曲がるリード
材料を用いることにより、第1図に示した従来例の場合
よpも、容易に接続されることになる。従って、従来よ
りも短かい時間でも圧接することが可能となり、従来発
生していた圧接時のクラック発生が改善される。Furthermore, as shown in FIG. 2, the metal bump 16 thus formed has a recess formed in its upper part by pressure contact with the bonding electrode. Therefore, the shape of the tip of the external lead wire 17 to be connected to this metal bump 16 should be bent in advance to match the shape of this recess, or a lead material that can be easily bent by the pressure during bonding may be used as a lead material. By using this, connection can be made more easily than in the conventional example shown in FIG. Therefore, it becomes possible to perform pressure welding for a shorter time than in the past, and the occurrence of cracks during pressure welding, which conventionally occurs, is improved.
第3−は本発明の他の実施例の要部を示す断面図である
。No. 3- is a sectional view showing a main part of another embodiment of the present invention.
本実施例は、金員バンプ16′を、第2図に示した実施
例において、熱圧着法により形成したAuリードからな
る金属バンプ16のリード線部分を、Alパッド13か
ら離れ°C1保護膜14上に達するだけの所要の長さを
残して切り取って構成したものである。In this embodiment, the metal bumps 16' are separated from the Al pads 13 by separating the lead wire portions of the metal bumps 16' made of Au leads formed by thermocompression bonding in the embodiment shown in FIG. It is constructed by cutting off the required length to reach the top of 14.
本実施例によると、リード線17′は第3図に示14上
の適切な箇所で金属バンブ16′と接続可能となり、接
続時に、半導体装置の信頼性を損うことがない。According to this embodiment, the lead wire 17' can be connected to the metal bump 16' at an appropriate location on the portion 14 shown in FIG. 3, and the reliability of the semiconductor device is not impaired during connection.
なお、以上の実施例の説明においては、ワイヤボンデン
グ法として熱圧着法を取上けたけれとも、超音波ボンデ
ング法などの他のワイヤボンデング法を用いても良いこ
とは言うまでもない。In the above description of the embodiments, although the thermocompression bonding method is used as the wire bonding method, it goes without saying that other wire bonding methods such as the ultrasonic bonding method may be used.
また、半導体基板としてシリコンを取上けだけれども、
これも他の半導体基板を用いた場合にも本発明が適用で
きることは言うまでもない。Also, although silicon is used as a semiconductor substrate,
It goes without saying that the present invention is also applicable to cases where other semiconductor substrates are used.
以上、詳細に説明したとおり、本発明の半導体装置は、
突起電極として、ワイヤポンチング法により接続された
リード線の一部分からなる上部金属(金属バンブ)を有
しているので、電気的2機械的に安定な突起電極を簡単
に形成できるとともに、外部リード接続時に従来発生し
ていたパープルプレイグツホワイトプレーグ及び表面保
護膜のクラックなどの発生が防止できる高信頼性の半導
体装置が得られるという効果を有している。As explained above in detail, the semiconductor device of the present invention includes:
The protruding electrode has an upper metal (metal bump) made of a part of the lead wire connected by the wire punching method, so it is easy to form an electrically and mechanically stable protruding electrode, and it is also easy to connect external leads. This has the effect of providing a highly reliable semiconductor device that can prevent the occurrence of purple plaque and white plaque and cracks in the surface protective film, which sometimes occur conventionally.
第1図は従来の半導体装置の一例の要部を示す断面図、
第2図は本発明の一実施例の要部を示す断面図、第3図
は本発明の他の実施例の要部を示す断面図である。
1・・・・・・半導体基板、2・・・・・・絶縁被膜、
3・・・・・・Alパッド、4・・・・・・表面保護膜
、5・・・・・・導電体、6・・・・−金員バング、7
・・・・外部リード、11・・・・・・半導体基板、1
2・・・・・・絶縁被膜、13・・・・・・Alパッド
、14・・・・・・表面保設膜、15・・・・・・導電
体、16.16’・・・・・・fiJバンプ、17.1
7’・・・・・・外部リード。
8/図
/’1FIG. 1 is a sectional view showing the main parts of an example of a conventional semiconductor device;
FIG. 2 is a sectional view showing a main part of one embodiment of the present invention, and FIG. 3 is a sectional view showing a main part of another embodiment of the invention. 1... Semiconductor substrate, 2... Insulating coating,
3...Al pad, 4...Surface protection film, 5...Conductor, 6...-Metal bang, 7
...External lead, 11...Semiconductor substrate, 1
2...Insulating coating, 13...Al pad, 14...Surface preservation film, 15...Conductor, 16.16'... ...fiJ bump, 17.1
7'...External lead. 8/Figure/'1
Claims (1)
上部金属がワイヤボンデング法により接続されたリード
線の一部分から構成されることを特徴とする半導体装置
。1. A semiconductor device having a protruding electrode, wherein an upper metal of the protruding electrode is formed from a portion of a lead wire connected by a wire bonding method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58141676A JPS6032335A (en) | 1983-08-02 | 1983-08-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58141676A JPS6032335A (en) | 1983-08-02 | 1983-08-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6032335A true JPS6032335A (en) | 1985-02-19 |
Family
ID=15297604
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58141676A Pending JPS6032335A (en) | 1983-08-02 | 1983-08-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6032335A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4742023A (en) * | 1986-08-28 | 1988-05-03 | Fujitsu Limited | Method for producing a semiconductor device |
-
1983
- 1983-08-02 JP JP58141676A patent/JPS6032335A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4742023A (en) * | 1986-08-28 | 1988-05-03 | Fujitsu Limited | Method for producing a semiconductor device |
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