JPS6032370B2 - PLL synthesizer type wireless equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a PLL (PhaseLMkedLMp) synthesizer type wireless device, such as a citizen's band (CB) transceiver, in which the PLL circuit has an unlock phenomenon (a phenomenon in which it stops oscillating at a predetermined oscillation frequency). During this period, the oscillation output from the PLL circuit is completely cut off.

Before explaining the present invention, a PLL synthesizer type CB transceiver will be briefly explained.

FIG. 1 is an overall block diagram of a CB transceiver using a PLL circuit in its oscillation circuit section. 1 is a common antenna for transmitting and receiving, 2 to 9 are each receiving system circuit, 2 is a high frequency amplifier, 3
is a first stage combiner, 4 is a first stage intermediate frequency amplifier, 5 is a second stage mixer, 6 is a second stage intermediate frequency amplifier, 7 is a detector, 8
is a low frequency amplifier, and 9 is a speaker.

Reference numerals 10 to 13 designate respective circuits of the transmission system, 10' being a microphone, 11 a low frequency amplifier, 12 a transmitting modulator, and 13 a high frequency amplifier.

14 is an oscillation circuit section composed of a PLL circuit, and the oscillation signal generated in the oscillation circuit section is sent to the first and second stage mixer 3.
, 5, are supplied to the modulator 12, respectively.

FIG. 2 is a concrete block diagram of the inside of the oscillation circuit section 14. As shown in FIG. In Figure 2, 15 is a reference frequency oscillator,
The oscillation output from the oscillator is applied to the second mixer 5 of the receiving system, and is also applied to the frequency divider 16 and mixer 17, respectively.

18 is a phase comparator, and the phase comparator receives the reference frequency signal from the reference frequency oscillator 15 through the frequency divider 16;
A voltage controlled oscillator 19 or a mixer 20 and a variable frequency signal via a programmable counter 21 are applied.

22 is the phase comparator 18 and the voltage controlled oscillator 19
A low-pass filter 23 provided between the mixer 20 is an oscillator that supplies a signal to the mixer 20.

Here, the oscillation frequency of the reference frequency oscillator 15 is f, the frequency division ratio of the frequency divider 16 is 1/ND, the oscillation frequency of the voltage controlled oscillator 19 is fo, the oscillation frequency f2 of the oscillator 23, and the frequency division ratio of the programmable counter 21. 1/NP, the phase comparator 18 has two inputs f, /ND and fo-
The phase of f2/NP is compared, a voltage proportional to the phase difference is generated to control the voltage controlled oscillator 19, and the synchronized loop of the PLL circuit operates so that the phase difference between the two inputs becomes zero.

Therefore, the frequency division ratio of the programmable counter 21 is 1/NP.
By changing , an output of a predetermined frequency can be obtained from the voltage controlled oscillator 19. 24 is connected to the voltage controlled oscillator 19 and the phase comparator 18 that constitute the PLL circuit, and when the voltage controlled oscillator 19 is out of lock, the oscillation is applied from the voltage controlled oscillator 19 to the transmitting modulator 12. This is a circuit that cuts off the output.

Note that this circuit will be explained later.

The output from the voltage controlled oscillator 19 is applied to the modulator 12 of the first transmission system via the circuit 24, and is also applied to the mixer 17.

An output signal having a frequency that is the sum of the oscillation frequencies of the reference frequency oscillator 15 and the voltage controlled oscillator 19 is obtained from the mixer, and this output signal is applied to the first mixer 3 of the receiving system. . In this type of CB transceiver,
, a period during which the PLL circuit is out of lock (a phenomenon in which the oscillation frequency from the PLL circuit is no longer locked to a predetermined frequency) (for example, the period until the oscillation frequency settles to a stable oscillation frequency when switching channels, or due to disturbances such as power fluctuations) It is necessary to prevent the transmitted radio waves from being radiated to the outside during the period from when the lock is released to when the next stable oscillation state is settled.

For this reason, the most commonly known PLL IC at present has a pulse (generally used as an unlock signal) whose width corresponds to the phase error between the reference frequency signal and the variable frequency signal applied to the phase comparator of the PLL circuit during the unlock period. A detection circuit is provided at the output side of the phase comparator, and conventionally the detection circuit generates the amp.

There is a known CB transceiver that utilizes a lock signal to cut off the oscillation output from the PLL circuit while the PLL circuit is out of lock, thereby preventing, for example, transmitting radio waves from being emitted. FIG. 3 is a circuit diagram of a main part of such a conventional CB transceiver. In FIG. 3, 25 is a detection circuit that generates an unlock signal when the PLL circuit 14 is out of lock, 26 is an output terminal of the detection circuit, and 27 is an integrator connected to the output state. Circuit 28 is a Schmitt trigger circuit controlled by the DC input voltage from the integrating circuit.

4A to 4D are waveform diagrams in A to D of FIG. 3 when the PLL circuit is out of lock.

Now, when the voltage controlled oscillator 19 of the PLL circuit 14 becomes unlocked, the fourth
An unlock signal having a waveform shown in FIG. 4A appears, and a DC voltage having an integrated waveform as shown in FIG. 4B is obtained from the integrating circuit 27.

The period during which this DC voltage exceeds the Schmitt level (T, ~
Transistor Q is turned on only after L and T3),
The oscillation output from the voltage controlled oscillator 19 constituting the PLL circuit 14 is cut off, and the oscillation output is prevented from being applied to the modulator 12, thereby preventing the transmission radio waves from being radiated.
The reference first receiver signal from the reference frequency oscillator 15 and the variable frequency signal from the voltage controlled oscillator 19 are applied to the phase comparator 18 constituting the PLU circuit 14.
If the phase error between the two signals is large, the unlock signal generated while the PLL circuit 14 is unlocked will have a wide width.

Therefore, in this case, the transmitted wave is completely blocked as shown after time L in FIG. 4D. However, the comparator 1
If the phase error between the reference frequency signal applied to the variable frequency signal 8 and the variable frequency signal is relatively small, there is a drawback that the transmission radio waves cannot be completely prevented from being radiated.

That is, when the phase error between the two input signals applied to the phase comparator 18 is small, the pulse width of the unlock signal corresponding to this phase error is narrow, and the output of the integrating circuit 27 reaches the Schmitt level as shown in FIG. 4B. or below the Schmidt level.

(Period BT2-L in FIG. 4) In this case, the transistor Q. is OFF and transistor Q2 is ON, so it is impossible to cut off the oscillation output from the PLL circuit 14, that is, to block the transmitted radio waves.

Ann like this. The narrow pulse width state of the clock signal always appears when the oscillation converges due to the transient response characteristics of the PLL circuit.
There is a period in which the phase error approaches zero several times before reaching a stable state, and there is a period in which transmission radio waves are emitted before the PLL circuit completely enters the lock state. In view of this, the present invention is designed to completely cut off the oscillation output from the PLL circuit even during the period when the PLL circuit is out of lock and the phase error between the two inputs to the phase comparator is small.
Examples of the present invention used in a transceiver are shown in Figures 5 to 6.
This will be explained according to the diagram.

In FIG. 5, 25 is a detection circuit that generates an unlock signal, 26 is an output terminal of the detection circuit, 27 is an integration circuit,
28 is a Schmitt trigger circuit as in the case of FIG. 3.

In the embodiment of FIG. 5, the Schmitt trigger circuit 2
An R-S flip-flop 29 that is inverted (reset) by the output from the flip-flop 8, and a time constant circuit that holds the output of the flip-flop at a predetermined level for a certain period of time, such as a monostable multipipe that starts after the flip-flop 29 is reset. 30 and the flip-flop 2
A switching circuit 31 controlled by the output of 9 is provided. Next, the operation of the circuit shown in FIG. 5 will be explained with reference to FIG. 6 as well. 6A to 6F are waveform diagrams at each point in FIG. 5. That is, A is a waveform diagram appearing at the output terminal 26 of the detection circuit 25, B is an output waveform diagram of the integrating circuit 27, C is an output waveform diagram of the Schmitt trigger circuit, D is an output waveform diagram of the R-S flip-flop 29, and E is a simple diagram. Stable multipipulator 3
0 is an output waveform diagram of the switching circuit 31, and F is an output waveform diagram of the switching circuit 31. During channel switching, etc., while the voltage controlled oscillator 19 of the PLL circuit 14 is out of lock, the phase error between the reference frequency signal and variable frequency signal applied to the phase comparator 18 exceeds a certain level. When the pulse width of the unlock signal exceeds a certain level, the output of the integrating circuit 27 exceeds the Schmitt level at time T4.

At this time, the output of the Schmitt trigger circuit 28 causes an R-S flip. Invert (reset) knob 29. Once the R-S flip-flop 29 is reset, the monostable multipipelator 30 resets the R-S flip-flop 2 for a period of time constant L of the monostable multipipelator.
The output of 9 is held at a constant level. The time constant To of the monostable multipipulator 30 is determined by the lock-up time of the voltage-controlled oscillator 19 of the PLL circuit 14 [the oscillation frequency of the voltage-controlled oscillator 19 is locked, and the oscillation frequency of the voltage-controlled oscillator 19 is locked to a predetermined frequency from a state The time required to complete the process is set to a slightly longer time (50 to 10 hsec).

The switching circuit 31 is the R-S flip-flop 2.
Since it is controlled by the output signal of 9 [the signal marked with ○ in FIG. It can completely prevent radio waves from being emitted to the outside. After the period of To has passed, R-S flip-flop 2
9 is set in green after the output pulse of the monostable multipipulator 30, and the oscillation output from the voltage controlled oscillator 19 is no longer cut off by the switching circuit 31 and is supplied to the modulator 12, and the transmitted electric wave is radiated to the outside. be done. At this time, the lock-up time of the voltage-controlled oscillator 19 has passed, so the voltage-controlled oscillator 19 is already in a completely locked state.

Incidentally, even if the voltage controlled oscillator 19 generates an unlock signal due to a slight fluctuation in the power supply while the voltage controlled oscillator 19 is in the locked state, the emission of the transmitted radio wave will not be blocked unless the output of the integrating circuit 27 exceeds the Schmitt level.

Furthermore, in the above embodiment, an example was explained in which the signal path was cut off to cut off the oscillation output from the PLL circuit, but the present invention is not limited to this embodiment, and the oscillation output may also be grounded. good.

Furthermore, in the above explanation, an example was given in which the transmitted radio waves were prevented from being radiated to the outside, but in the same way, in the receiving system, when the PLL circuit is out of lock, it is possible to prevent the signal from being received for a certain period of time. to prevent malfunctions.

As described above, according to the present invention, the PLL circuit. When a lock-up occurs, the oscillation output from the PLL circuit is blocked for a period longer than the lock-up time of the PLL circuit by using a pulse signal generated according to the phase error of the two inputs that is applied to the phase comparator. Since a circuit is provided, it is possible to prevent transmitted radio waves from being radiated to the outside and from receiving undesired signals during a period when the PLL circuit is not in a locked state, such as when switching channels.

[Brief explanation of the drawing]

Fig. 1 is an overall block diagram of a CB transceiver that uses a PLL circuit as an oscillation circuit, Fig. 2 is a block diagram of a PLL circuit equipped with a circuit that blocks the oscillation output of the PLL circuit, and Fig. 3
The figure is a circuit diagram showing a conventional example of a circuit that cuts off the oscillation output of a PLL circuit, Figures 4A to D are waveform diagrams at each point in Figure 3, and Figure 5 is a block diagram showing the main parts of the present invention. Figure, Figure 6 A~
F is a waveform diagram at each point in FIG. 14...PLL circuit, 18...phase comparator, 19...voltage controlled oscillator, 25...detection circuit, 27...integrator circuit, 28... ... Schmitt trigger circuit, 29 ... R-S flip-flop, 30 ... Monostable multipipulator, 3
1...Switching circuit. Figure 4 Figure N Ship Figure 3 Figure 5 Figure 6

Claims (1)

[Claims] 1. When a PLL circuit is used in the oscillation circuit section and the PLL circuit goes out of lock, the phase error of the two input signals applied to the phase comparator constituting the PLL circuit is In a PLL synthesizer wireless device in which a detection circuit that generates a pulse having a width of A PLL synthesizer type wireless device, comprising a circuit that blocks oscillation output from the PLL circuit for a period longer than the lock-up time of the PLL circuit. 2. The PLL synthesizer wireless device according to claim 1, wherein the oscillation output that is cut off when the PLL circuit goes out of lock is the oscillation output that is applied to a transmitting modulator. 3. The PLL synthesizer type wireless device according to claim 1, wherein the two input signals applied to the phase comparator are a reference frequency signal and a variable frequency signal. 4. When the PLL circuit loses lock, the circuit that uses the output of the detection circuit to cut off the oscillation output from the PLL circuit for a period longer than the lock-up time of the PLL circuit is an integrating circuit connected to the detection circuit. a Schmitt trigger circuit controlled by the output of the integrating circuit; a flip-flop reset by the output from the Schmitt trigger circuit; and a time constant for holding the output of the flip-flop at a predetermined level for a period longer than the lock-up time. 2. The PLL synthesizer type wireless device according to claim 1, comprising: a switching circuit; and a switching circuit controlled by the output of the flip-flop. 5. The PLL synthesizer type wireless device according to claim 4, wherein the time constant circuit is a monostable multivibrator.