JPS6032375B2 - Code conversion method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase modulation method, particularly a three-phase PSK (Phase
The present invention relates to a code conversion method for determining the correspondence between three phases 0, 2, and 3 in a shift key modulation method and digital baseband data.

Conventionally, in the 2n (n is an integer) PSK modulation system, there has been a one-to-one correspondence between a signal vector and binary digital input data, known as a so-called Gray code. On the other hand, the 3-phase PSK modulation method has been known as a modulation method with a better error rate than the 2n-phase PSK, but how can binary digital data be associated with the three phases of the 3-phase PSK modulation method? has not been determined so far.

An object of the present invention is to create a new correspondence between the above-mentioned signals in the three-phase PSK modulation method, and to rationally perform the three-phase PSK modulation.

The present invention will be explained below with reference to the drawings. Figure 1 shows 3-phase P
The vector diagram of the SK signal is shown, and each phase is
◇2, J3 are off by 1200. FIG. 2 is a block diagram showing the configuration of a three-phase PSK modulator to which the present invention is applied, in which 21 is a binary digital data input, 22 is a code conversion circuit according to the present invention, and 23, 24, and 25 are code conversion circuits. 26 is a modulation circuit, 27 is 3
Figure 3 shows a phase PSK modulated output. Here, the digital data 23, 24, 25 specify the phase signal that the modulation circuit 26 should send out. That is, for example, the codes 23, 24,
When 25 is 1, 0, 0, the modulation circuit 26 outputs the phase of 1 in FIG.
, 1, 03 is output. In this way, the modulation circuit 26 can be easily configured using, for example, a switch, so that only the signal corresponding to the "1" bit of the input digital data is selected from among the three predetermined signals having mutually different phases. be able to. Since it is not possible to make a direct one-to-one correspondence between binary input data and ternary signal phases, the phases of m time slots are made to correspond to n-bit binary input data. For example, for 3 bits of binary input data, 2 time slots (for example, J,, 2
) shall correspond. All binary input data must be in carrier phase, ? 2, ma3, natural numbers m and n must satisfy 2n total 3m. There are an infinite number of m and n that satisfy this relationship, but to simplify the explanation, the case where m=2 and n=3 will be described below. The 3-bit binary data represents 8 different states, and the 3-phase phase of 2 time slots represents 9 different states.

Table 1 shows an example of the correspondence between 3-bit binary input data and 2 time slots of 3-phase signals.

Table 1 and FIG. 3 are time charts showing these responses.

In the figure, 31 indicates binary input data having a 3-bit configuration, and 32 indicates a transmission phase obtained by converting the code into a corresponding 3-phase signal. In order to realize the code conversion shown in Table 1, as is clear from the explanation of FIG.
A code conversion circuit 22 is required which uses the value input data to create 8-phase signals output from the modulation circuit. This code conversion is shown in Table 1◇
,=(1,0,0),g2=(0,1,0),? 3=(
0, 0, 1), and such a code conversion circuit can be easily realized. FIG. 4 is a block diagram showing a more specific example of the configuration of the three-phase tower K modulator according to the present invention. In the figure, 41 represents binary input data, and 42 represents binary input data.
Haku. 43 is a serial-parallel conversion circuit, 44
, 45, 46 are the data converted in parallel, 47, 48
is the code conversion logic circuit, 49, 50, 51 is the code output that determines the phase of time slot 1, and 52, 53, 5 is the code output that determines the phase of time slot 1.
4 is a code output for determining the phase of time slot 2, and these 49 to 54 correspond to 23, 24, and 25 in FIG. Further, 55, 56, and 57 are switches 58, 59, and 60' that alternately change the signs of time slots 1 and 2 at twice the speed of the clock signal having a period of 3 bits in 31 in FIG. The outputs of these switches are shown below. Here, the logic circuits 47 and 48 will be explained.

Now, 44, 45, and 46 parallel binary data are respectively d,
, also, the binary data of d3, 49, 50, 51 are respectively a,, a2, a3, and 52, 53, 54 are q, Q, b3.
The logic circuit 47 is expressed as follows {1)
performs logical operations. a. =d.・d30d.・d2・
d3 a2=d.・Raju d.・d2・d3
...{11a3=d.・Also, the logic circuit 48 performs the logical operation of the following formula (2): oq=a. ...mo.d3 Q=a2.d3 0a2.d3...
{2} Wide = d, d momme 30 d.・d2・d3 Note that the circuit configuration for performing these calculations is well known, so a description thereof will be omitted here.

As described above, the output 5 code-converted by the circuit shown in FIG.
8, 59, and 60 as a three-phase phase modulation circuit 26 shown in FIG.
When connected to the outputs 58, 59, and 60, signals G, , and 2 and 3 are outputted as shown in Table 1.

According to the present invention described above, m(1<m<n, 2n<
3m) Since 2n states out of the 3m possible states of the 3-time slot SK correspond to each other, three-phase bad K modulation with a good error rate can be rationally realized.

[Brief explanation of the drawing]

Figure 1 is a vector diagram of a three-phase K signal, Figure 2 is a block diagram showing an example of the configuration of a three-phase K modulator according to the present invention, and Figure 3 is the relationship between input and output of the modulator. FIG. 4 is a block diagram showing the configuration of the code conversion circuit according to the present invention. In the figure, 22 is a code conversion circuit, 26 is a modulation circuit, and 31
is the input of the modulator, 32 is the output, 47 and 48 are the logic circuits,
55, 56, and 57 indicate switches. Hiroshi 28 Tsutomu Z crab meeting tooth trench 4 crab

Claims (1)

[Claims] 1 One piece of n-bit binary data is expressed as m(1<m<n, 2
Consisting of 3 bits (^n<3^m), 1 bit is "1"
is converted into a binary signal with 2 bits of "0" as a phase designation signal, and m signals designated by "1" of the designation signal among three predetermined signals with mutually different phases are converted. 1. A code conversion method, wherein each possible state of the n-bit binary data corresponds to a different state of the m 3-bit signals.