JPS6033327B2 - Frame synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION When attempting to transmit multi-channel data using one transmission line, it is necessary on the receiving side to perform frame synchronization in order to separate each channel.

The present invention relates to a circuit that performs this frame synchronization (hereinafter simply referred to as synchronization). Conventionally, when synchronization is lost, for example, a mismatch pulse is generated and the pulses are accumulated, and when a certain value is exceeded, it is determined that synchronization has been lost and synchronization is carried out.

However, in this type of system, synchronization protection was insufficient and synchronization stability was often unsatisfactory. FIG. 1 is an example of a multiplexed data format and mat.

In the transmission of such multiplexed data, PN (fixed pattern pseudo noise) is used to separate each channel.
It is necessary to use a synchronous code whose autocorrelation function, such as a code, has a sharp pattern. Further, as a condition required for this synchronization circuit, it is important that it be quick and accurate when entering into synchronization, and that once it is brought into synchronization, it is difficult to lose synchronization. Furthermore, the synchronization code used for synchronization should be designed to minimize errors such as not being able to receive a synchronization pattern when it is being sent, and to minimize errors such as misidentifying it as a synchronization code when no synchronization pattern is being sent. It is necessary to make it such that In the present invention, a PN code with a sharp autocorrelation function is used as a synchronization pattern, and synchronization is performed when the synchronization pattern is completely received.
Once synchronization has been achieved, errors up to n bits are allowed, and once synchronization is achieved, a time gate is applied to the bit position where the PN code occurs so that only the PN code is detected. This reduces the probability of synchronization to almost zero, which is the first and second synchronization protection means among the features of the present invention. The present invention will be explained in more detail below. In the example below, the PN code has a 15-bit structure (m=15), and there is a 1-bit error (n=1).
This is the case where the following is allowed. Figure 2 is an example of a PN code with 15
This is the case when it consists of bits.

Each bit is in the multiplexed data format.
As shown in the figure, when the number of channels is 7, the second
They are inserted in the order shown. One round is made of 8×15=120 bits, and one frame is composed of these 120 bits.

That is, in the PN code, all 15 bits are inserted one bit at a time every eighth bit in one frame, which is repeated for each frame. Note that if the PN code is m bits and the number of channels is k, one frame is (k+1)×m bits and P
N codes are inserted once every frame. FIG. 3 is a block diagram of a configuration example of a frame synchronization circuit embodying the present invention.

In this figure, 1 is 120 bits [generally (k+1)
xm bits] shift register, the received data DR is sequentially shifted by the receiving clock C and inputted. That is, it is for storing received data and detecting frame synchronization. 2 is generally m bits. In this example, a 15-bit PN code pattern (Figure 2) is stored in R.
In OM (Read Only Memory), the bits (Q, ,
Q, Q, 7,...Q,. 3) is output to an exclusive OR (EX-OR) circuit 3 provided with 15 bits.

The EX-OR circuit 3 outputs 0 when the two inputs match, and outputs 1 when they do not match, as shown in the following truth table. Since exclusive OR is performed for each corresponding bit (15 bits in total), the output of the circuit 3 is 15 bits.
When the exclusive OR truth table, that is, the bit position of the PN code in the received data matches the pattern in the memory ROM2, all outputs of the circuit 3 become zero.

The output of EX-OR circuit 3 is sent to adder circuit 4. Circuit 4 is a 1-bit full adder circuit group that performs addition to convert how many bits out of 15 bits are 1, that is, the number of PN code reception errors, into a q-bit binary number (q is an integer greater than or equal to 0). In this example, the circuit outputs 4 bits. If all inputs are zero, that is, the received data matches the PN code, it will output (0000)2, and if there is a 1-bit difference, it will output (
0001) Outputs 2. Furthermore, if everything is different (
1111) Outputs 2. The output of the circuit 4 is input to a magnitude comparator 5. Magnitude comparator 5 uses 4-bit binary comparison, that is, A input (
Ao ~ A3) and B input (Mr ~ &) are compared, but only & of the B input is determined by the Q output of the synchronization flag circuit 10 (a flip-flop circuit that indicates the synchronized state), and as described later. It becomes 1 when synchronization is achieved, and becomes 0 when synchronization is lost. B
B, , B2, and B3 during input are always 0. A input and B
When the inputs are compared and they match, the A=B output terminal outputs 1, and when A is greater than B, the A>B output terminal (however, this output is not used) becomes 1, and conversely, when A<B. When A<B terminal outputs 1. Next, 6 and 12 are AND
(gate) circuits, 7 and 11 are OR (gate) circuits, 8 is generally k11 bits, in this example an 8-bit IJ counter, and 9 is a mono multivibrator.

The ring counter 8 receives and counts the received clock C, and outputs the position of the synchronizing PN code from a predetermined position, for example, the first bit position in this example. Figure 4 is a time chart of the output waveform of the ring counter 8. When synchronization is established, Q, is PN.
The symbol Q2 indicates the position of channel 1, and Q8 indicates the position of channel 7, and is used to separate each channel. Out of these, Q and the output are input to an AND circuit 12 through an OR circuit 11. - Returning to the explanation of the magnitude comparator 5, the B input will be (0000) 2 when out of synchronization as described above, and (00) when synchronization is established.
01) Becomes 2.

The reason for this is that since the received data is multiplexed, the probability of occurrence of 1 and 0 is usually equal and can be treated as noise.
In the case of a 15-bit PN code, data matching the PN code will appear among the received data with a probability of 1/5. This is an average of 5/4800 = 32768/4800 when the data transmission rate is 4800 baud/second (BPS).
This occurs once every =6.825 seconds, indicating that each channel will generate a burst error if frame synchronization is erroneously achieved. To prevent such yielding, once synchronization is established, the output of bit position Q of the PN code of the 8-bit ring counter 8 is input to the OR circuit 11. Another input to the OR circuit 11 is the Q output of the synchronization flag 10, and assuming that this Q output becomes 0 when synchronization is achieved, one input to the AND circuit 12 is the Q output of the ring counter 8. becomes. Another input of the AND circuit 12 is O
As for the output of the R circuit 7, when the data transmission rate is 480 PS, the output of the OR circuit 7 becomes 1 only by a difference of 1/480 when the data matches the PN code. However, when synchronization is achieved, the output of the OR circuit 7 is only used as the output of the AND circuit 12 (this becomes the synchronization pulse) only at the bit position where the PN code is placed (once for every 8 bits), and as mentioned above The probability that synchronization is erroneously established from received data is reduced. That is, circuits 5 to 12 have a circuit configuration including a third synchronization protection circuit using a temporal gate. The operation of this protection circuit will be explained later, but if you provide a time protection circuit that only outputs a synchronization pulse at the bit position of PN, the output of the AND circuit 12 will be at the bit position where the PN code is included. Since the output of the OR circuit 7 is sampled only at , the probability of the above-mentioned erroneous synchronization can be reduced to almost zero. However, the bit yield rate (for example, 1
Since the data is protected with 0 (approximately 5), the PN code naturally also causes errors, and in that case it is determined that the synchronization has been lost and synchronization is re-established. For example, when the bit error rate is 10-5, the probability that a PN code (15 bits are included in one frame) cannot be correctly received is theoretically 1.5×10-4; This means that an error occurs on average once every time a frame is received, resulting in loss of synchronization. To improve this, it is necessary to set the B input of the magnitude comparator 5 to 0001) once synchronization is achieved as described later.

In the above, the PN code is made up of 15 bits (m=15), and 1
Although the case where a bit error (n=1) is allowed has been mainly shown, cases where n is 0, 2, 3, . . . , etc. will be supplemented as follows.

When n=0, it means that the PN code in the received data completely matches the predetermined pattern, and n=0.
When n=1, errors up to 1 bit are allowed; when n=2, errors up to 2 bits are allowed. Similarly, this can be summarized as shown in the following table. Table n = 0, that is, a complete match: In this case, if an error occurs in the bit position of the PN code after synchronization pull-in, it is determined that the synchronization is out of synchronization, so the synchronization stability is 1/16 compared to the case of 1-bit error correction. become.

When n=2, ie, 2-bit error correction is performed: In this case, the B input of the magnitude comparator 5 is connected as shown in FIG. 5 instead of FIG. 3. In this case, n=
121/16=7. The stability of needle sound synchronization is improved. When n=3: Connect the B input of the magnitude comparator 5 as shown in FIG. (B
The input connection is changed according to the 4-bit binary number of n) In this case, the stability of synchronization is improved by 3 stitches compared to the case where n=1. Similarly, if the number of error corrections is increased to n = 4, 5, etc., the stability of synchronization will be improved, but on the other hand, when the bit errors are extremely reduced, for example when switching lines Since it becomes difficult to lose synchronization, the probability of successive errors (burst errors) increases.
The value of n must be determined based on the transmission quality of the line used and the value passed through that line.

The above protection circuit will now be explained.

When the A input and the 8 input are equal, the magnitude comparator 5 outputs an output to the AND circuit 12 through the OR circuit 7.
1", and when A<B, 1 input of the AND circuit 6 is 1, that is, only when the Q output of the synchronization flag 10 is 1 (synchronized), the signal is sent through the AND circuit 6 and the OR circuit 7.
It has been mentioned before that the circuit 12 outputs "1". A
The other input of the ND circuit 12 is the Q output of the synchronization flag 10 (which becomes 1 only when out of synchronization) via the OR circuit 11 or the Q output of the ring counter 8, so the output of the AND circuit 12 during synchronization. That is, the (frame) synchronization pulse becomes the reset pulse of the ring counter 8 and the set input of the mono-multivibrator 9, and further becomes the IJ set, ie, R input, of the synchronization flag 10 (flip-flop). This synchronization pulse increases the data transmission rate by 4
If there are 80 ship PSs, it will be output once every 120/4800 = 25 hs, but the output waveform of the ring counter 8, which is reset every synchronization pulse as described above, is as shown in Figure 4, where Q, is the position of the PN code. , so the position of Q and O
Only when the outputs of the R circuit 7 match, a synchronizing pulse is generated and input to the mono multivibrator (MMV) 9. This M
MV9 can be retriggered and its output pulse width is P
Since it is a little longer (50hs + Q) than the length of 2 frames of N code (28hs x 2), synchronization is achieved and 28
As long as there is a set input to MMV9 every hs, the Q output of MMV9 will not change to 1 and the S input to the synchronization flag 10 will not occur. In addition, the R input is given to the synchronization flag 10 by the synchronization pulse, so when synchronization is established (synchronization pull-in), the Q output is ○, the Q output is 1, the output to the OR circuit 1 1 is 0, and the output to the AND circuit S And the output of the magnitude comparator 5 to & becomes 1. Therefore OR
The output of the circuit 7 becomes 1 both when the A input from the adder circuit 4 to the comparator 5 matches the B input and when A<B.
(However, since the B input is 0001, the A input is 0000.
or 0001. ) Next, when the synchronization is lost and there is no synchronization pulse from the AND circuit 12, MMN9
Since the output pulse length of is longer than two frames, the Q output of MMV9 will not be inverted to 1 and will not be considered out of synchronization unless the PN code is received incorrectly for two consecutive frames.

This is the operation of the third synchronization protection circuit. Also, if the PN code cannot be received for two or more consecutive frames, MM
The Q output of V9 changes to 1, and the Q of the synchronization flag 10 becomes 1 and Q becomes 0, and it is determined that synchronization has been lost, and the output of the OR circuit 7 is always A.
The signal can now be input to the ND circuit 12. In this case, since the output of the OR circuit 7 is only when A=B, only the correct synchronizing pulse is output and synchronization is reestablished. The effect of such a synchronization protection circuit is to increase the stability of the synchronization circuit by maintaining synchronization for a certain period of time without immediately losing synchronization even if a burst error occurs. To illustrate this effect as an example, it is not determined that synchronization is lost unless two or more of the 15 bits of the PN code are incorrect. This means that when the bit error rate is, for example, 10-5, the frame error rate (PN code cannot be received correctly) The probability) is theoretically 2.1×10-8, which is a four-digit improvement compared to the case where determination is made only based on perfect matches.
Also, when the synchronization is out, the B input of the comparator 5 is set to (0000), that is, a complete match between A and B input and output is required, but the reason for this is that when synchronization is brought in, all received data is compared, so it is possible to accidentally synchronize. This is because the probability that each bit of the PN code is completely matched and the probability of correcting a 1-bit error is approximately 1/16 of the latter. As explained in detail above, in the synchronous circuit equipped with the three synchronization protection circuits of the present invention, once synchronization is established, it is extremely difficult to lose synchronization, reducing the probability of erroneous synchronization being achieved when entering synchronization. This is a major achievement and has great practical effects.

It should be noted that conventional circuits usually operate in a contradictory manner, in that making it difficult to lose synchronization increases the probability of erroneously achieving synchronization.

[Brief explanation of the drawing]

Figure 1 is an example of a multiplexed data format, Figure 2 is an example of a 15-bit PN code, Figure 3 is an example of the configuration of a frame synchronization circuit embodying the present invention, and Figure 4 is an example of a frame synchronization circuit according to the present invention. The output time chart of the ring counter in Figure 3, Figure 5 is the connection diagram of the B input of the magnitude comparator in Figure 3 when n = 2, and Figure 6 is the connection diagram of the B input of the magnitude comparator in Figure 3 when n = 3.
It is a connection diagram of the B input of the magnitude comparator in the figure. 1...120-bit shift register, 2...
...15-bit PN code memory circuit (ROM), 3
...Exclusive OR circuit, 4...1-bit addition circuit group, 5...Magnitude comparator, 6, 12...AND circuit, 7, 11...OR circuit , 8... 8-bit ring counter, 9... Mono multivibrator (MMV), 10... Synchronization flag circuit (flip-flop). Figure 1 Figure 2 Figure 4 Figure 3 Figure 5 Figure 6

Claims (1)

[Claims] 1 m bits in a fixed pattern (m=2^i-1, i is 1
Receiving side of multiple k-channel data transmission (k is an integer greater than or equal to 1) that uses a pseudo-noise code (PN code) as a synchronization code and inserts all bits in sequence every k+1 bits for each frame. As a frame synchronization circuit,
A shift register that stores received data sequentially inputted by a reception clock and generates an output for every (k+1) bit in (k+1)×m bits, a storage circuit that stores an m-bit pattern of a PN code, and the shift register. of(
k+1) The output for each bit and the corresponding bit output of the above storage circuit are respectively two inputs, and when the two inputs match, a binary code of 0 is output, and when they do not match, a binary code of 1 is output. Exclusive OR (EX-OR) circuit for bits and the number of times when the output of the above EX-OR circuit is 1, that is, the number of reception errors of the PN code, are divided into 2 of q bits (q is an integer greater than or equal to 0). An adder circuit that converts into a base code, a q-bit input from this adder circuit (this is taken as the A input), and a 1 bit input at the time of synchronization.
Also, take the reset side output (■) of the synchronization flag circuit that outputs 0 when synchronization is lost, and set the other bits to 0 (q)
Compare the size with the bit input (this is input B) and select A.
A comparison circuit that outputs 1 when =B and when A<B, and a first AND circuit whose two inputs are the output of this comparison circuit when A<B and the output of the synchronization flag circuit.
A first OR circuit has two inputs: the output when A=B of the comparison circuit and the output of the first AND circuit, and counts the reception clock and generates an output for each bit (k+1).
Bit ring counter and PN of the above ring counter
A second OR circuit takes the output of the bit corresponding to the sign position and the set output Q of the synchronization flag circuit as two inputs, and the outputs of the first OR circuit and the second OR circuit take the outputs as two inputs. A second AND circuit that serves as a reset pulse for the ring counter, a mono-multi vibrator that is set by the synchronization pulse that is the output of the second AND circuit, and generates a pulse with a width slightly longer than the length of two frames; It is equipped with a synchronization flag circuit consisting of a flip-flop which uses the vibrator reset output (■) as a set input and the output of the second AND circuit described above as a reset input, and when synchronizing, the reception code of the m-bit PN code and the code of the storage circuit are used. A comparator circuit detects a complete match between the two, and after synchronization is pulled in, it is determined that synchronization is achieved if m−n bits or more match, and the synchronization is maintained and synchronization is achieved. A frame synchronization circuit is characterized in that it generates a synchronization pulse only at a bit position where a PN code is generated, and does not determine that the synchronization is out of synchronization unless the reception of the PN code is erroneous for two consecutive frames.