JPS6034126B2 - Digital signal function conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal function conversion circuit. In this specification, a digital signal function conversion circuit refers to a circuit that converts a digital input signal using a predetermined function and obtains a coded digital output signal. For example, pulse code modulation (hereinafter referred to as PCM)
In order to display the level information carried by PCM digital data in dB level during recording, etc., the input digital data is converted into a function,
In this case, it is a circuit that performs logarithmic conversion and then obtains a coded digital output signal, and in this case, it is a digital signal logarithmic conversion circuit, which is a logarithmic compression circuit that logarithmically compresses the analog signal level. corresponds to In conventional digital signal function conversion, as shown in FIG. 1, a random logic gate circuit 1 is used to convert a digital input signal into a function, and then encodes the signal to obtain an output converted into a digital output signal. However, when using the conventional digital signal function conversion circuit as described above, it is difficult to freely change the conversion function, and the random logic gate circuit becomes complicated. This method has drawbacks such as the need to set equal intervals or to ignore the lower bits of the digital input signal at the expense of accuracy. The present invention has been made in view of the above, and it is an object of the present invention to provide a digital signal function conversion circuit that eliminates the above-mentioned drawbacks. According to the invention, this purpose is obtained by dividing the maximum and minimum values of the digital input signal into a number corresponding to the number n of bits of the desired output code signal corresponding to the inverse function of the conversion function. A storage circuit that stores digital values at each division point, a digital comparator that compares the digital value output from the storage device with a digital input signal value, and receives the output of the digital comparator as input. a shift register; and an address for sequentially selecting a digital value stored in the storage circuit in response to an output value of the digital comparator for each output from the digital comparator to the shift register and outputting it to the digital comparator. This is achieved by providing a specified control circuit and obtaining an n-bit digital output signal from the shift register. The present invention will be explained below using examples. FIG. 2 is a block diagram of one embodiment of the present invention. In this embodiment, the conversion function is a logarithmic function, for example, P
An example will be explained in which 14-bit digital data recorded as a commercial is logarithmically converted to a 4-bit binary digital output signal. In FIG. 2, 2 is a storage circuit such as read only memory (ROM) or read/write memory (RAM). For example, as shown on the horizontal axis in FIG. 3, the inverse function of the conversion function that aims to convert between the minimum value DM and the maximum value DMA of the digital input signal, since the conversion function that is aimed at in this example is a logarithmic function. Divide into desk sections according to an exponential function. In this embodiment, the number n of bits of the output digital signal to be obtained is 4, so it is divided into 16. These dividing points are B and C respectively? ..., P, each division point B, C, ...
- The digital value of the digital input signal value of P is stored in the storage circuit 2. For example, in Fig. 3, Z is a logarithmic function approximated by 16 broken lines, and the origin on the vertical axis corresponds to the maximum value DM, and the logarithm value DMA' is vertically correlated to the maximum value DMA. Each point B', C',...P' is taken on the axis and the space between the origin of the vertical axis and DMA' is equally divided into one box on the vertical axis.
, dividing points B, C, ...P can be defined on the machine axis, and the digital value of the digital input signal value at each dividing point B, C, ...P, that is, between DMI and DMA. The digital values of digital input signal values at division points B, C, . . . P, which are divided into 16 according to an exponential function, are stored. Hereinafter, the digital values responsive to the dividing points B, C, . . . P may be indicated as B, C, . . . P, respectively. Furthermore, the storage circuit 2 is a digital comparator (hereinafter simply referred to as a comparator) that outputs one of the digital values B, C, ...P of each dividing point specified by the address designation signal from the control circuit 3.
Output to. Comparator 4 has a 14-bit digital input signal and storage circuit 2
The input is the digital value output from , and the two input values are compared. Now, if the digital value from the storage circuit 2 to the comparison device 4 is SR, and the digital input signal is S2, then the comparator 4
is the high potential output (hereinafter referred to as "high potential output") when SRmiSz
(indicated by "1" and low potential output indicated by "0").
5 is a 4-bit serial input that receives the output of comparator 4;
This is a parallel output shift register, and the control circuit 3 performs addressing to sequentially select digital values stored in the storage circuit 2 in response to the output of the comparator 4. For convenience of explanation, the minimum value DM1 and the digital values B, C, . . . Therefore, the minimum value DMI is

[0000], B is [0001], G is [
0010], . . . P is written as [1111] to indicate the order of the dividing points. Therefore, when the digital input signal is input to the comparator 4, the contents of the shift register 5 are cleared, and the control circuit 3 specifies the address where the digital value 1 [1000] of the division point 1 of the memory circuit 2 is stored. do. Here, the digital input signal value S2 and the digital value 1 [1000] output from the storage circuit 2 are compared by the comparator 4. As a result, when the digital input signal S2 is between the digital value 1 and when 1≦S2, the comparator 4 outputs an output “1” to the shift register 5. Further, when 1<S2, the comparator 4 outputs an output "0" to the shift register 5. Next, the control circuit 3 specifies the storage address of the digital value in the storage circuit 2 as the next comparison data based on the first comparison result inputted to the shift register 5. When the first comparison result is “1”, the control circuit 3 selects the address where the digital value M [1100] of the division point M is stored.
When the first comparison result is "0", the control circuit 3 specifies the address where the digital value E [0100] of the division point E is stored, and compares the digital input signal value Sz with the digital value M or E. A second comparison is made between. It goes without saying that these timings are performed in synchronization with the shift pulse given to the shift register 5. The shift pulse is selected to have a frequency approximately six times higher than the frequency at which digital input signals are sequentially input to the comparator 4. The first pulse clears the contents of the shift register 5, and the second to fifth pulses clear the contents of the shift register 5. The comparison result is input with the pulse , and the contents of the shift register 5 are outputted to the output terminal OUT with the sixth pulse. The result of the second comparison is input to the shift register 5 in the same manner as in the above case. Similarly, a third comparison and a fourth comparison are subsequently performed. In this case, the comparator 4 is transferred from the storage circuit 2 to the comparator 4 by address specification from the control circuit 3.
The digital values output to are as shown in Fig. 4, and the digital values B[0001], B[0001],
One of C[0010], . . . P[1111] is selected and output. This state is shown in FIG. In Fig. 4, 2 is indicated in brackets [ ] below the frame.
The base number is a 4-bit symbol that indicates the order of each division point, and this symbol determines the order of the digital values output from the memory circuit 2, which are then selected in a dendritic manner by the address designation signal of the control circuit 3, based on the comparison result. It will become clear. Furthermore, the symbols enclosed in a frame indicate the digital value of each division point. Further, in FIG. 4, the solid line between the frames indicates the selection path when the output from the comparator 4 to the shift register 5 is "0", and the broken line indicates the selection path when the output is "1". When the fourth comparison is completed as described above, a 4-bit digital output signal is provided to the shift register 5. By reading out the contents of this shift register 5, the function conversion for the digital input signal S2 is completed, and the same function conversion is performed for the next digital input signal as well. Here, the first comparison result of the comparator 4 is the most significant bit of the digital signal, that is, the 4th bit, the second comparison result is the 3rd bit, and the third comparison result is the 2nd bit. The fourth comparison result is also the digit of the 1st bit digital signal, which is shown in parentheses in Figure 4, and the output "1" between each frame is
”, “0” arranged in sequence. For example, if the digital input signal Sz falls between the digital values P≦Sz<DMA at the dividing point, then [1111
] If the digital output of [1110] is a value falling between 0≦S2<P, the digital output of [1110] is obtained as the output signal, and the digital input signal is similarly converted by a logarithmic function and then converted into a 4-bit digital signal. It is converted to a value and output. First, a specific example of the control circuit 3 will be explained. Now, the digital values B, C, ...P of the division points are 1, M, E, 0, K,
If G, C, P, N, L, J, day, F, D, B are stored in the order of memory circuit 2, the control circuit 3 receives a clear signal and a clock signal (shift pulse). From the storage circuit 2 shown in FIG. An address signal can be obtained from the control circuit 3 to sequentially select the output data in a tree-like manner. Also,
Even if the comparator 4 is set so that the output of the comparator 4 becomes "0" when Sz≦SR, the same configuration as described above can be achieved. In this case, as described above, the digital input signal S2
If it is a value that falls between the digital value P<S2SDM of the division point, a digital output of [1111] will be obtained, and if it is a value that falls between 0<S2≦P, a digital output signal of [1110] will be obtained. Become. Also, the minimum value DM, and the maximum value D
Divide the distance between MA and MA by (2n-1), that is, 15, and make 18
If the dividing point B at the time of division matches the minimum value DM, then 1
Even in the case of five divisions, a similar configuration can be made and the same effect will be achieved. Further, although the above example is a case where the digital output signal is 4 bits, a similar configuration can be used when it is desired to obtain a 5 bits digital output signal. In this case, one digital output signal is obtained by comparing the number of comparisons of the comparator 4 five times with respect to one digital input signal. The same applies to the case of n bits. Further, although the above embodiment is a case in which a logarithmic function is used as the conversion function, conversion can be similarly performed in the case of other functions. In this case, the digital value of the dividing point stored in the memory circuit 2 becomes the value converted by the conversion function. In addition, although the above embodiment was explained using an example in which the vertical axis is divided at equal intervals as shown in FIG. . In short, it is sufficient that the storage circuit 2 stores digital values of division points determined according to the inverse function of the conversion function. As described above, according to the present invention, a digital input signal can be functionally converted, the conversion is accurate, and the range and interval of dB values can be arbitrarily selected when used to display a dB level. Furthermore, if a memory circuit with a large capacity is used, it is possible to arbitrarily select division by switching between several levels, for example, division into 32 points at intervals of two ships, 32 points at intervals of one ship, etc.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional digital input signal function conversion circuit, and FIG. 2 is a block diagram of an embodiment of the present invention. FIG. 3 is a diagram for explaining the operation of the present invention. FIG. 4 is a diagram for explaining selection of output data from the memory circuit. FIG. 5 shows an example of a control circuit. Tsuku diagram. 2...Memory circuit,
Mr. 3... Control circuit, 4... Comparator, 5... Shift register. Figure 1 Figure 2 Figure 3 Figure 5 Figure 4

Claims (1)

[Claims] 1 Number of bits n of the output signal to be obtained by following the inverse function of a predetermined conversion function between the minimum value and maximum value of the digital input signal
a storage circuit that stores a digital value at each division point obtained by dividing into a number corresponding to the number of responses to the signal; and a digital comparator that compares the magnitude of the digital value output from the storage circuit with the value of the digital input signal. a shift register which receives the output of the digital comparator as an input; and a digital value stored in the storage circuit in response to the output value of the digital comparator for each output from the digital comparator to the shift register. 1. A digital signal function conversion circuit, comprising: a control circuit for sequentially selecting and specifying addresses to be output to a digital comparator; and obtaining an n-bit digital output signal converted by a conversion function from the shift register.