JPS6034760B2 - Electronic musical instrument keyboard circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a keyboard circuit for an electronic musical instrument that performs digital processing.

Conventionally, as a method for keyboard circuits, there is a method for detecting the press and release states of each key on a keyboard, as disclosed in US Pat. As a result, each key is sequentially scanned from the bass to the treble or from the treble to the bass, and the pressed state of the key is extracted as a time-division multiplexed signal.

A register group is provided for extracting and storing the octave and pitch name signals of the pressed keys from the time-division multiplexed signal. The number of such registers is generally limited by the maximum number of key presses, and is often set to ten or more. Since writing to the registers is performed using the time-division multiplexed signal, even if the octave and note name signals of the key have already been written to one of the registers, the time-division multiplexed signal The multiplexed signal repeats and contains the signal corresponding to the key. Therefore, control is required to avoid writing the same contents as the registers that have already been written. In addition, when the key is released, the key press signal simply disappears, so extract the octave and note name signals of the key for which the press signal has disappeared, search for a register in which the same content as the signal is written, and check the contents It was necessary to erase the register or provide it as a fall start signal to the envelope control circuit corresponding to the register.

An object of the present invention is to provide a keyboard circuit for an electronic musical instrument that can easily distinguish and control key depression and key release.

In order to achieve the above object, the keyboard circuit of the electronic musical instrument of the present invention includes a multiplexer that specifies a specific key code for each key on the keyboard and detects the input key code and the pressed state of the corresponding key. a detection circuit, a key code generation circuit that sequentially generates a key code for each of the keys, a shift register that stores the key code, and a comparison between the output key code of the shift register and the output key code of the key code generation circuit. a comparison circuit that outputs a match signal if they match; a cycle control circuit that distinguishes and controls key-on cycles and key-off cycles; and an output key code of the key code generation circuit and an output key code of the shift register.
a key code selection gate that selects a code at the time of the key-on cycle and the key-off cycle and outputs the selected code to the detection circuit; a selection circuit that selects an output key code of the key code generation circuit and an output of the shift register in response to the above, and the detection circuit detects that a key that has not been pressed yet is newly pressed during a key-on cycle. Detecting and storing the key code in the shift register, detecting that a key that has already been pressed during a key-off cycle is newly pressed, and erasing the contents of the storage register corresponding to the key code of the key. It is characterized by being controlled as follows.

The present invention will be described in detail below with reference to examples.

In Figure 1, 1 is a keyboard, 2 is a multiplexer, 3 is a selection gate, 4 is a selection circuit, 5 is a shift register, 7 is a key code generation circuit, and 8 is a comparison circuit. It is indicated by.

The binary key code generated by the key code generation circuit 7 corresponds to each key on the keyboard. For example, if the number of keys is 61, the binary key code is composed of 6 bits.

For a pressed key, the key code is stored in the shift register 5. The operation of this circuit is divided into a key-on cycle and a key-off cycle, and in the key-on cycle,
The key code generated by the key code generating circuit 7 is applied to the multiplexer 2 through the selection gate 3. The multiplexer 2 selects the pressed state of the key corresponding to the key code, and if the key is pressed, the selection circuit 4 selects the event signal EV.
give to The key code generated by the key code generation circuit 7 is also given to the selection circuit 4, and the selection circuit 4'
The key code is written into the shift register 5 in response to the event signal EV. If the key is not pressed, the event signal EV is not generated and no key code is written to the shift register 5. Further, the key code corresponding to the key being pressed is stored in a shift register 5, and the shift register 5 circulates through the selection circuit 4 every time the output key code of the key code generation circuit 7 changes.

The output of the shift register 5 is compared with the key code from the key code generating circuit 7 in a comparator circuit 8, and if they match, a match signal is given as an increment signal to the key code generating circuit 7, and the output key code is used as the next key code. Move. Key scanning is not performed depending on the matching key code.
During a key-off cycle, the key code generation circuit 7 stops, and the selection gate 3 transfers the key code from the shift register 5 to the multiplexer 2 according to a control signal from the cycle control circuit 9.
give to

In the key-off cycle, since the key code of the pressed key is stored, the key is scanned only for that key code. If the key is not pressed, an event signal BV2 is generated from the multiplexer 2, and the contents of the address in the shift register 5 where the key code is stored are erased. If the key continues to be pressed down, the event signal EV2 will not be generated. Key-on cycles and key-off cycles occur alternately.

The number of addresses in the shift register 5 is controlled by the number of priority channels (not shown), and if key codes are stored in all addresses in the shift register 5, there is no need to search for a new key to press, so the key-off cycle Repeat only. In this way, the shift register 5 circulates and outputs in both key-on and key-off cycles. Figure 2 shows keyboard 1 and multiplexer 2 in Figure 1.
FIG.

As an example, assume that there are 61 keys.

Since the number of keys is 61, the number of bits of the binary key code is 6 bits, and key codes (000001) to (111101) are made to correspond to each key. 211a,
21-b is a decoder.

The 6-bit binary key code given from the key code selection gate 3 is divided into upper and lower 3 bits, and each decoder outputs "1" to only one of the 8 output lines for the input 3-bit key code. ``Give a signal. 21-a, 2
22 by combining 8 lines from 11b
One AND gate among -1, 22-2, . . . , 22-61 is opened.

If the key designated by the 6-bit binary key code is pressed, the OR gate 23 outputs a "1" level signal, and if the key is not pressed, it outputs a "0" level signal. FIG. 3 is a detailed explanatory diagram of main parts related to the key-on cycle and key-off cycle in FIG. 1.

In the same figure, a key code generation circuit 7, a comparison circuit 8, a cycle control circuit 9, a selection circuit 4, and a shift register 5 are each surrounded by broken lines and correspond to the same numbers in FIG. shown. FIG. 4 is a time chart. First, at the time of a key-on cycle, a clock generated by the clock A31 in the cycle control circuit 9 shown by the broken line is given to the shift register (main body) 36 and latch circuit 37 in the shift register 5 shown by the broken line via the selection gate 33, The key code data in the main body 36 is circulated by this clock.

Further, this clock is frequency-divided by a 1/1 frequency divider 34, and the 1/mA clock generated by the clock A is applied via an OR circuit 48 to a key code counter 35 in the key code generation circuit 7 shown by a broken line.

The key code generated by the key code counter 35 corresponds to each key on the keyboard, and is sent to the selection gate 3 through the register 38. Multiplexer 2 from selection gate 3
If the key corresponding to the key code given to is pressed, an event signal "1" is generated. Also, the flip within the cycle control circuit 9. Since the flop 52 outputs a "0" level signal during the key-on cycle, this signal and the pento signal are combined with the exclusive OR circuit 4 in the selection circuit 4 shown by the broken line.
0 to the AND circuit 42. Each word of the shift register 36 is composed of 7 bits, which are divided into 1 sign bit and 6 key code bits. The sign bit is a bit indicating that a key code is written in each address, and is simultaneously written as a "1" level signal when data is written. Therefore, the output of the shift register has a sign bit of “0” at an empty address.
Therefore, the exclusive OR circuit 40 outputs "1" when the sign bit is "0", opens the AND gate 42, and sets the flip-flop (FF) 43.

When the flip-flop (FF) 43 is set, the monostable multipipulator (MM) 44 outputs a pulse. FIG. 4 shows a time chart from the exclusive OR circuit 40 to which the event signal described above is input to the monostable multipipelator (MM) 44.

That is, in contrast to the clock shown in figure a, the clock shown in figure b is 1/m. If select gate 3 than multiplexer 2
If the key corresponding to the key code given to is pressed, the event signal d in the figure is generated, and the sign bit (S.B) of the output of the shift register 36 at that time is as shown in c in the figure. , the output of the flip-flop 43 is shown in the figure e.
The output of the monostable multipipulator (M.M) is shown by f in the figure. The key code of the sign bit "1" inputted from the register 38 to the selection gate 46 is inputted to the selection gate 45 by the pulse from the monostable multipipulator 44.
is selectively output and written into the latch circuit 37.

The shift register (main body) 36 consists of m-1 words,
Together with the latch circuit 37, it forms a circular loop of m words.

m is the number of priority channels. The contents of the register 38 are branched and input to the 11 adder 39 in the comparator circuit 8 shown by the broken line, and 11 is added, and this output key code and the shift register 3 are input.
The key codes from 6 are compared in a comparison circuit 47. In this case, if the key code given from the register 38 to the multiplexer 2 via the selection gate 3 is N, then the next key code N+1 is output from the eleven adder 39. If the key is pressed, it is shifted and written in the register, and there is no need to detect the key press in the key-on cycle.
Therefore, if the key code N+1 and the key code from the shift register match, a matching pulse will be sent to the key code counter 3.
5 is advanced by one, and the output of the key code counter 35 is N+2.
Then, by the next 1/m clock, the register 38 becomes N.
+2 is written, and the eleven adder 39 moves to N+3. In this way, the register 38 shifts from N to N+2 and does not output N+1. In other words, multiplexer scanning for key code N+1 is omitted.

In this way, the above operation is performed for all key codes. Since the last key code is (111101), the key code counter 35 counts up to the key code (111110). When the output of the key code counter 35 becomes the key code (111111), the AND gate 5
3 is a cycle control flip-flop that outputs a "1" signal. Set the knob and move on to the key-off cycle. In the key-off cycle, the cycle control flip-flop 52
The selection gate 33 selects the key-off cycle clock B due to the inversion of . The key code data of the shift register (main body) 36 and latch circuit 37 is circulated by the clock B. The output of the shift register (main body) 36 is applied to the multiplexer 2 through the selection gate 3 to detect the pressed key. If the key is released, the event signal “0”
" level is generated, and the EXOR gate 40 outputs a "1" signal. This signal is applied to the selection gate 45 through the AND gate 53. On the other hand, the selection gate 46 selects the GND (ground) signal in the key-off cycle, and the selection gate 45
is giving to Therefore, this signal selects all bits 0 and writes all bits 0 to the latch circuit 37. If the key continues to be pressed, no event signal will be generated. The above-mentioned operation is not used for all the addresses, and when it is completed, the 1/m clock resets the flip-flop 52 via the AND gate 51, ending the key-off cycle and moving on to the key-on cycle. Also, shift register (main body) 36
The output of is given to an m-bit shift register 49.

Both shift registers are shifted by the same clock. Therefore, if key codes are written to m addresses of the shift register (main body) 36, all sign bits will be “1”.
” At this time, the output of the shift register 49 is all “
1", and the NAND circuit 50 outputs a "0" level signal. Therefore, since the AND gate 51 is closed, the flip-flop is not reset by the 1/m clock, and the key-off cycle can be repeated again. In other words, the NAND circuit 50 outputs a "0" level signal. A 0'' level signal means that all channels are occupied, and only the key-off cycle is repeated.As explained above, according to the present invention, when a key that has not already been pressed is newly pressed. The control is divided into a key-on cycle, which detects a key that has already been pressed, and a key-off cycle, which detects that a key that has already been pressed is newly pressed.
By time-divisionally outputting individual keys, keys can be detected using a relatively simple configuration, whereas conventional keys require complicated configurations and controls to distinguish between pressed and pressed keys. The key code for the key can be output in a time-division manner over m priority channels.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing the configuration of an embodiment of the present invention, FIGS. 2 and 3 are detailed explanatory diagrams of main parts of the embodiment of FIG.
The figure is a waveform diagram for explaining the operation of a part of Fig. 3, and in the figure, 1
2 is a keyboard, 2 is a multiplexer, 3 is a selection gate, 4 is a selection circuit, 5 is a shift register, 7 is a key code generation circuit, 8 is a comparison circuit, and 9 is a cycle control circuit. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1 A detection circuit consisting of a multiplexer that specifies a specific key code for each key on the keyboard and detects the pressed state of the key corresponding to the input key code, and a key code that sequentially generates the key code of each key. a generation circuit, a shift register that stores the key code, a comparison circuit that compares the output key code of the shift register with the output key code of the key code generation circuit and outputs a match signal if they match, and a key-on cycle. a cycle control circuit that controls a key-off cycle and a key-off cycle, and a key that selects an output key code of the key code generation circuit and an output key code of the shift register during the key-on cycle and the key-off cycle, respectively, and outputs the selected keys to the detection circuit. A code selection gate is connected to the input of the shift register to form a memory loop with the shift register, and the output key code of the key code generation circuit and the output of the shift register are connected in response to a control signal of the cycle control circuit. and a selection circuit for selecting a key that has not yet been pressed during a key-on cycle, and causes the shift register to store the key code upon detecting that a key that has not yet been pressed during a key-on cycle is pressed; 1. A keyboard circuit for an electronic musical instrument, characterized in that the keyboard circuit is controlled to detect that a previously held key has been newly lifted off and erase the contents of the storage register corresponding to the key code of the key.