JPS6034821B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor memory devices, particularly insulated gate field effect transistors (hereinafter referred to as MISFETs or simply FETs).
The present invention relates to a static type memory in which memory cells are configured using .

The static memory has a configuration as shown in FIG. 1, for example.

In the figure, resistance R, FETM. A first inverter in which a resistor R2 and an FET M2 are connected in series and a second inverter in which a resistor R2 and an FETM2 are connected in series are cross-connected to each other such that the output of one is applied to the input of the other. This memory cell has the advantage that a resistor such as polycrystalline silicon, which can have a high resistance value in a small area, can be used as a load, and the size of the memory cell can be reduced. In such a memory cell, information is written and read through gate FETs M3 and M controlled by a write/read signal JR. Storage of information is performed by turning on one of the FETMs, M2 and turning the other off due to positive feedback of the circuit.

In order to reduce the power consumption of the memory cell, the resistance values of the resistors R, , R2 used as the above-mentioned loads are selected as follows.

That is, for example, when one FETM of the memory cell is in an on state, the potential of its drain Vw is
The potential at the drain VN of FET M2 in the off state must be at a low level that turns off the FET M2.
M, must be at a high level which turns it off.

Each drain potential can be considered to be accumulated as a charge, for example. In the above state, charge is accumulated in the gate capacitance C of the FETM, but not in the gate capacitance C2 of the other FETM2. In this state, the charge accumulated in the gate capacitance C of FETM, decreases due to the leakage current of FETM2,M. In order to create a memory cell with low power consumption, the maximum resistance value of the resistor R2 connected to the output point VN side is set to a value low enough to compensate for the loss of charge due to the leakage current. It is necessary to The maximum resistance value of the resistor R connected to the other output point VM side is
・Value is FETM. It is set to a large value because it is necessary to reduce the current flowing through this inverter when the inverter is turned on. In other words, the upper limit of load resistance R,, R2 is FET
The lower limit is determined by the current consumption of the entire memory cell, which is affected by the current flowing through this resistance. A resistor that satisfies these conditions has a relatively high value (for example, 1 to 1 IQ), and cannot be practically realized by a diffused resistor in a semiconductor integrated circuit IC.
It is made of a polycrystalline silicon layer that can easily have a relatively high resistance value.

In this polycrystalline silicon layer, the resistance value of a part of the polycrystalline silicon layer used as a wiring layer of a MIS type semiconductor device is controlled by ion implantation, and the part is used as a high-resistance layer. However, when the load resistor is constructed from the polycrystalline silicon layer, it is relatively difficult to control the resistance value in terms of process.

In other words, normally when making a polycrystalline silicon layer high in resistance, it is done by controlling the amount of ion implantation as described above, but the relationship between the amount of ion implantation and the resistance value at this time is As shown in the figure, since the curve is inversely proportional and changes rapidly, the resistance value changes greatly (Ay) with a small change in the ion implantation amount (△x), making it difficult to control it to an appropriate value. Become. Further, even if it is possible to control the resistance to an appropriate value through the process, there is a problem in that the resistance value decreases depending on the usage conditions of the product because the temperature coefficient of the polycrystalline silicon layer is large. For this reason, in memory cells that use a polycrystalline silicon layer as a load resistor,
This makes it difficult to reduce current consumption and retain high-level information. The present invention has been made to solve the above-mentioned problems, and its purpose is to obtain an optimal resistance as a load of a memory cell.

Another object of the present invention is to provide a semiconductor memory device including memory cells with low current consumption and a small amount of accumulated charge dissipated. The present invention will be specifically explained below using Examples.

FIG. 3 is a plan view of a memory cell showing one embodiment of the present invention. Note that, for convenience of explanation, this figure shows a plan view without the insulating layer and wiring layer to be finally formed. Each of the above layers will be explained later. In addition, the elements shown in the circuit diagram of FIG. 1 and FIG. 2 corresponding to FIG.
The elements are indicated using the same reference numerals. In FIG. 3, reference numeral 1 denotes a p-type silicon substrate, and the surface of the substrate other than the element formation region is covered with a thick silicon oxide film 2 as an insulating film.

The silicon oxide film 2 has a thickness of approximately 1.2 mm, for example, in order to prevent an undesired channel layer from being induced on the surface of the silicon substrate 1 due to a wiring layer stored on this oxide film 2 or undesired charges. The thickness shall be . 91a, 91b, 92a, 92b and 9 whose planar shapes are indicated by diagonal lines
Reference numeral 3 denotes an n+ type silicon layer with a relatively high impurity concentration, which is formed on the surface of the silicon substrate 1 to serve as the source region, drain region, and semiconductor wiring region of the skin SFET.

92c and 92d indicated by diagonal lines in a direction different from the diagonal lines above.
is an n-type silicon layer with a low impurity concentration formed on the surface of the silicon substrate 1, although it does not essentially need to have a low impurity concentration. 6 and 7 shown in RBI are MISF
A polycrystalline silicon layer serves as a gate electrode, wiring layer, and resistance layer of ET.

For example, the polycrystalline silicon layers 6 and 7 have a thickness of about 3500
The thickness is said to be A.

3a to 3d, each range is indicated by a combination of a broken line and a solid line indicating the texture of the polycrystalline silicon layer.
is a thin silicon oxide film formed between the polycrystalline silicon layer 6 or 7 and the silicon substrate 1 as the gate insulating film of each MISFET, and its thickness is, for example, about 1
000A.

3e and 3f are thin silicon oxide films formed between the polycrystalline silicon layer 7 and the n-type silicon layer and the n+ type silicon layer, and the thickness thereof is equal to that of the silicon oxide film 3.
The thickness is made the same as that of a to 3d.

The polycrystalline silicon layer 6 extends over the thick silicon oxide film 2 and the thin silicon oxide films 3a and 3b, and is electrically insulated from the silicon substrate 1 and the n+ type silicon layer.

On the other hand, polycrystalline silicon layer 7 is electrically connected to n+ type silicon layers 92a and 92b, respectively, at portions 41a and 41b surrounded by two-dot chain lines.

Such electrical contact is made by direct contact between the n+ type silicon layers 92a, 92b and the polycrystalline silicon layer 7, although not particularly limited thereto. The polycrystalline silicon layer 7 includes a thick silicon oxide film 2 and thin silicon oxide films 3c to 3f except for the portions 41a and 41b.
It extends upward.

The n+ type silicon layer 91a extends to a portion that almost coincides with the end 6a of the polycrystalline silicon layer 6, and similarly, the n+ type silicon layer 92a extends to a portion that almost coincides with the end 6b. ing.

The MISFETs M3 and M4 as shown in FIG.
Configures the drain region and source region of ETM3.

Polycrystalline silicon layer 6 on silicon oxide film 3a constitutes a gate electrode. Similarly, n+ type silicon layers 91b, 92
b, the polyconjunctival silicon layer 6 on the gate insulating film 3b constitutes the drain region, source region, and gate electrode of the MISFET M4, respectively.

The n+ type silicon layers 92a and 93 and the polycrystalline silicon layer 7 on the gate insulating film 3c constitute the drain region, source region, and gate electrode of the MISFETM, respectively.

The n+ type silicon layers 92b and 93 and the polycrystalline silicon layer 7 on the gate insulating film 3d constitute the drain region, source region, and gate electrode of MISFET M2, respectively.

The polycrystalline silicon layer 7 has a common portion 71 and an individual portion 7.
It consists of 2,73 pieces.

Of the individual portions 72, the portion surrounded by the two-dot chain line 8a between the common portion 71 and the contact portion 41a is of n-type with a relatively low impurity concentration, and constitutes a resistor R.

Similarly, of the individual portions 93, the portion surrounded by the two-dot chain line 8b is an n-type with a relatively low impurity concentration, and constitutes the resistor R2.

The portions of the polycrystalline silicon layer 7 other than the resistive portion and the polycrystalline silicon IJ layer 6 are made of n-type with a high impurity concentration, and are made to have a sufficiently low resistance as wiring or a gate electrode.

The entire surface of the silicon substrate 1 shown in FIG. 3 is covered with an insulating film 10 having openings 111a, 111b and 112 as shown in FIG. Without layer 12, layer 14 is extended.

The wiring layer 12 is in contact with the n+ type silicon layer 91a at the opening portion 111a, and the wiring layer 13 is in contact with the n+ type silicon layer 93 at the barrier portion 112.

Furthermore, the wiring layer 14 is in contact with the n+ type silicon layer 91b at the barrier portion I11b. The n+ type silicon layers 91a, 91b are connected to the input/output terminals V, V2 via the wiring layers 12, 14, and the n+ type silicon layer 93 is connected to the ground point of the circuit via the wiring layer 13. .

The polycrystalline silicon layer 6 is connected to an input/output signal source OR,
A common portion 71 of polycrystalline silicon layer 7 is connected to power supply Vcc. In the above structure, the resistance R. Since the portion of the polycrystalline silicon layer 7 that is formed is placed on the n-type silicon layer 92c via the thin silicon oxide film 3e, it receives the electric field from this silicon layer 92c.

．． Similarly, the portion of the polycrystalline silicon layer 7 that becomes the resistance R2 is the n-type silicon layer 92d.
receives an electric field from

In FIG. 3 or FIG. 1, the potentials VM and V at each node
N becomes lower than the potential of the positive power supply Vcc due to the voltage drop across the resistors R, , R2.

In this case, depending on the stored memory content, for example, if MISFETM is in the on state and MISFET M2 is in the off state, the potential VM is close to the ground potential of the circuit, and the potential VN is close to the power supply potential. become.

Therefore, a relatively large potential difference appears between the potential of each portion of the polycrystalline silicon layer 7 constituting the resistor R and the potential VM. On the other hand, due to the OFF state of MISFET M2, only a small potential difference appears between the potential at each point of the polycrystalline silicon layer 7 constituting the resistor R2 and the potential VN.

Due to the electric field based on the above potential difference, the resistance R,,R2
The resistance value of the polycrystalline silicon layer 7 that constitutes the portion changes. FIG. 9 shows a schematic diagram for explaining the resistance change of the polycrystalline silicon layer 7 constituting the resistor R when the MISFET M is in the on state.

In the above, n+
Type silicon layer 92a is at approximately ground potential, and therefore n-type silicon layer 92c is also at ground potential. On the other hand, the polycrystalline silicon layer 7 is at each point at a positive potential determined by the resistance drop.

The n-type silicon layer 92c is different from the polycrystalline silicon layer 7.
The polycrystalline silicon layer 7, which has a relatively negative potential and forms an interface with the oxide film 3e, has the n-type silicon layer 9.
2c, a negative electric field of a magnitude corresponding to the relatively large potential difference between the two and 2c is applied.

Depending on the magnitude of the negative electric field, negative charges are removed from the vicinity of the interface of the polycrystalline silicon layer 7, and positive charges are introduced to the vicinity of the interface, thereby expanding a depletion layer or an inversion layer.

As described above, the polycrystalline silicon layer 7 is of the n-type, and the substantial cross-sectional area of the portion through which electron current flows is reduced by the depletion layer and the inversion layer.

The portion of the polycrystalline silicon layer 7 designated by this resistance R has a relatively low impurity concentration compared to other portions, and the substantial cross-sectional area of the current path is relatively greatly reduced by the negative electric field. . As a result, the resistance value of resistor R, is MISFE
It changes greatly depending on the on state of TM.

On the other hand, due to the off-state of the MISFET, the potential difference between the polycrystalline silicon layer 7 and the n-type silicon layer 92d in the portion where the resistance R2 is increased is small, as described above.

Therefore, the substantial cross-sectional area of the current path in the polycrystalline silicon layer 7 in the above-mentioned portion hardly decreases, and its resistance remains relatively constant. In this way, M in the on state
The resistor in series with the ISFET changes to a high resistance, reducing the current in this series path and sufficiently reducing the drain current determined by the conductance of the MISFET and the resistance value of the resistor.

On the other hand, the resistor in series with the MISFET in the OFF state has a low resistance value, and only a small voltage drop occurs with respect to the above-mentioned leakage current.

Therefore, a sufficient zero potential is applied to the gate of the MISFET in the on state. In this way, in the device shown in Fig. 3, the values of the resistors R, , R2 change in a favorable direction during circuit operation, so the load resistance, which is determined by taking into account characteristic variations during manufacturing and characteristic fluctuations during use, can be kept relatively low. It operates with low current consumption even when the resistance value has to be increased.

The above-mentioned memory device is manufactured using selective oxidation technology and self-alignment technology, for example, as described below, although it is not particularly limited.

First, a p-type silicon substrate 1 is prepared.

Next, by using a well-known selective oxidation technique using a silicon nitride film as a selective oxidation mask, an n-type silicon layer, an n+
A thick silicon oxide film 2 is formed on the surface of the silicon substrate 1 except for a region where a mold silicon layer and a gate insulating film of a MISFET are to be formed (hereinafter, the region where these layers and films are formed will be referred to as an element formation region).

The selective oxidation mask is removed to expose the surface of silicon substrate 1 in the element formation region.

A thin silicon oxide film 3 is formed on the exposed surface by thermal oxidation.

The planar shape of the thin silicon oxide film 3 in this step is as follows:
The result is as shown by the solid line in FIG. Next, a photoresist film serving as a mask for impurity ion implantation is applied onto the oxide films 2 and 3.

By exposing and developing the photoresist film, the fourth
The oxide films 2 and 3 are exposed in the portions shown by two-dot chain lines 5a and 5b in the figure, that is, in the portions where a resistor will be formed later and in the vicinity thereof.

Phosphorus as an n-type impurity is ion-implanted into the surface of the silicon substrate 1 through the silicon oxide film to form n-type silicon layers 92c and 92d.

FIG. 7a shows a cross section of a portion corresponding to the section AA in FIG. 4 during ion implantation. The above ion implantation is performed at an energy level that does not allow the ions to penetrate through the photoresist film 20 and the thick silicon oxide film 2. Therefore, the surface of the p-type silicon substrate 1 is converted to n-type only in a limited range by the photoresist film 20 and the thick silicon oxide film 2. Next, the photoresist film 20 is removed and a new photoresist film is formed.

This photoresist film is exposed and developed to expose the silicon oxide films 2 and 3 in the portions indicated by two-dot chain lines 4a and 4b in FIG.

The oxide films 2 and 3 are etched using the photoresist film as an etching mask.

In this case, the etching amount is defined as the thickness of the thin oxide film 3).
By making them equal, only the diagonally shaded portion of the silicon substrate surface in FIG. 4 is exposed. After removing the photoresist film, as shown in FIG. 7b, the entire surface is coated with CVD.
An impurity-free polycrystalline silicon layer 21 is deposited by a method.

By ion implantation of phosphorous, the polycrystalline silicon layer 21 is made n-type, and its sheet resistance value is set as the sheet resistance value of the portions which will later be designated as resistances R, , R2. This ion implantation is performed at an energy of 100 KeV, for example.
It is carried out under the conditions of 3 x 1 and 3/s. The polycrystalline silicon layer 21 is selectively etched away using a photoresist film to form a polycrystalline silicon layer 7.

Using the polycrystalline silicon layer 7 as an etching mask, the exposed silicon oxide film is
Only etching. In this step, as shown in FIG. 7c, which is a partial cross section corresponding to the portion in FIG. Next, a silicon oxide film is formed on the entire surface by CVD.

As shown by two-dot chain lines 8a and 8b in FIG.
, R2, the silicon oxide film is selectively etched away, leaving portions of the polycrystalline silicon layer 7 designated as R2.

In FIG. 7d, the silicon oxide films left after the above etching are shown as 22 and 23. Although the widths of the silicon oxide films 22 and 23 are not particularly limited, it is preferable that the widths be set so that the silicon substrate 1 is exposed at the ends thereof, as shown in FIGS. 3 and 7d.

Note that in the above etching, the silicon oxide film 22
, 23 is exposed again. Next, the exposed polycrystalline silicon layers 6 and 7
Then, phosphorus is diffused into the silicon substrate 1 as an n-type impurity. In this step, an n+ type silicon layer is formed on the silicon substrate 1 as shown at 92a in FIG. 7d. Further, the polycrystalline silicon layer not covered with the silicon oxide films 22 and 23 becomes n-type with sufficiently low resistivity. Next, an insulating film 10 such as phosphor glass is formed on the entire surface, and holes 111a and 111b are formed.
, 112, deposited with metal such as aluminum, and selectively etched to form a wiring layer 12 and 14, thereby completing the structure as shown in FIG. 6 or 8.

The invention is not limited to the foregoing embodiments.

That is, in the embodiment described above, a case has been described in which the conductivity type of the polycrystalline silicon layer is n-type, but the present invention is not limited to this, and a polycrystalline silicon layer having p-type conductivity may be used. In this case, as the n-type diffusion layer serving as the variable bias electrode, it is necessary to use the diffusion layer 92b to which the voltage of the output point VN of the other inverter is applied, contrary to the case of the above embodiment. With such a structure, the resistance value can be lowered. The reason is explained as follows.
When the output point VN of the second inverter is at a low potential due to the ON state of MISFET M2, a negative electric field is applied to the p-type polycrystalline silicon through the gate oxide film 3f on the n-type diffusion layer 92d at this low potential. applied to the layer. This electric field causes carriers to accumulate in the p-type polycrystalline silicon layer, increasing the number of carriers and lowering the resistance value. That is, the resistors R, , R2 are each controlled by the output voltage of the other inverter, and act to reduce the value of the resistor to which a particularly high voltage is applied. Therefore, even if the values of the load resistances R, , R2 are high due to variations in process conditions, the MI in the OFF state due to the low output voltage of the other inverter in the operating state
Since it acts to lower the resistance value of the load connected to the SFET, it is possible to prevent stored information from disappearing due to leakage current. In addition, in the above embodiment, an n-channel type MIS
Although we have shown the case where FET is used as a memory element,
A similar effect can be obtained when a p-channel FET is used.

In this case, the polarity of the power supply is reversed. According to the present invention, it is possible to obtain an optimal resistance as a load of a memory cell, and by using such a resistance, a memory cell can be realized that can reduce current consumption and stably retain stored information. A semiconductor memory device including the present invention can be obtained.

The present invention can be widely applied to static type memo IJI.

[Brief explanation of drawings]

Figure 1 is a basic circuit diagram of a static type memory cell.
Figure 2 is a correlation curve diagram between ion implantation amount and resistance value.
The figure is a plan view of a memory cell according to an embodiment of the present invention, FIGS. 4, 5, and 6 are plan views in each manufacturing process, FIGS. 7 a to d are sectional views in each process, and FIG. 9 is a sectional view of a completed device, and FIG. 9 is a sectional view of a variable semiconductor resistance element according to an embodiment of the present invention. M, ~M4...FET, R,,R2...Resistance, C,,C
2... Capacity, 9 1 a, 9 1 b, 92 a to 92 d,
93...n+ type diffusion layer, 6,7...polycrystalline silicon layer,
111a, 111b, 112.・Through hole, 3a~
3e...Gate oxide film, 12-13...Aluminum wiring layer, 2...Thick oxide film, 1...P-type substrate. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 8 Figure 7 Figure 9

Claims (1)

[Claims] 1. In a semiconductor memory device in which a circuit including two inverters each having a load resistor and a FET connected in series is connected to each other so that the output of one is applied to the input of the other on a single semiconductor substrate, A semiconductor memory device characterized by having bias means for increasing the resistance value of a load resistor connected in series with an FET that is turned on and decreasing the resistance value of a load resistor connected in series with a FET that is turned off.