JPS6034823B2 - Semiconductor integrated storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated memory device suitable for high density storage.

Memory cells with an MIS structure (M includes polysilicon, etc.) that utilize the charge accumulated in the parasitic capacitance of diodes can achieve lower power consumption and higher density than memory cells with a latch configuration of multiple transistors. .

In particular, one MIS structure diode and one insulated gate transistor (hereinafter MIS (M
(including polysilicon etc.) called transistor)
Among the memory cells that utilize the charge accumulated in the parasitic capacitance of these MIS structure diodes, the type realized using diodes is superior in achieving high density, so it is often used in large-capacity semiconductor integrated memory devices. It is being said. However, in this type of semiconductor integrated memory device, in addition to the MIS diode region for charge storage and the insulation isolation region, each memory cell has at least one MIS transistor region, and outside of this S-transistor, the MIS A region of digit lines connected to the structure diodes was required.

Furthermore, if a diffusion layer similar to the source/drain diffusion layer of an MIS transistor is used as a digit line, a wiring area for this diffusion layer is required, but this wiring area is ignored in a semiconductor integrated memory device. It occupied an impossible area. When a layer other than the diffusion layer is used as a digit line, a contact hole area is required, but this contact hole area still occupies a considerable area due to alignment margin. Therefore, there is a limit to high density in the conventional memory cell using one MIS structure diode and one MIS transistor. An object of the present invention is to provide a semiconductor integrated memory device which occupies a small area per memory cell, requires only an MIS structure diode region for storing electric charge and an insulating region, and which is easy to achieve high density and mass production. The goal is to provide the following.

A semiconductor integrated memory device according to the present invention includes a second conductivity type layer formed in a part of the surface of a first conductivity type semiconductor substrate and serving as an address line or a lead line to the address line; It is characterized by comprising a thin insulating layer formed on a part of the surface of the thin insulating layer, and a conductive layer formed on the surface of the thin insulating layer and serving as a digit line or a lead wire to the digit line.

In the present invention, binary information is stored by storing charges in a parasitic capacitance of an inversion layer formed in a second conductivity type layer constituting a MIS structure diode.

That is, in the MIS structure diode, the inversion layer can be formed by maintaining an appropriate relationship between the potentials of the surface side electrode and the second conductivity type layer. Binary information is stored depending on whether it is saved or not. In the present invention, the read operation is performed by applying a bias to the second conductivity type layer through an address line or directly to the first conductivity type semiconductor substrate, the second conductivity type layer that is not inverted, and the inversion layer. This is done by creating a bipolar transistor operation between and injecting charge carriers of the first conductivity type into the inversion layer.

At this time, the behavior of the potential of the inversion layer differs depending on whether or not it has previously stored charge carriers of the first conductivity type, so this is read out through the surface-side electrode. The write operation utilizes the fact that after the read operation, the inversion layer can be formed or erased by setting the potentials between the front side electrode and the second conductivity type layer in an appropriate relationship.

When the inversion layer is erased, the charge carriers of the first conductivity type injected into the inversion layer during the read operation flow out into the semiconductor substrate of the first conductivity type through the second conductivity type layer which is not inverted, and the charge carriers are left in the inversion layer. can form an inversion layer. When an inversion layer is formed, it is possible to form an inversion layer in which charge carriers of the first conductivity type injected into the inversion layer during a read operation are stored as they are. This is how binary information is written. Next, details of the structure adopted in the present invention and its operation will be explained with reference to the drawings.

FIG. 1 is a sectional view showing the structure of a memory cell portion in one embodiment of the present invention.

This embodiment includes an N-type semiconductor substrate 11, a P-type diffusion layer 12 (hereinafter referred to as P-well) formed on the surface of the semiconductor substrate, and a conductor layer forming the surface-side electrode of a MIS structure diode formed on the P-well surface. 13, a thin insulating layer 14 constituting the MIS structure, a P-type low resistance buried layer 15 connected to the P well and serving as an address line, and a thick field insulating film 16 forming an insulating isolation region. Here, the conductor layer 13 also serves as the digit line, and the MIS structure diode composed of the P well 12, the thin insulator layer 14, and the conductor layer 13 is constructed so that the threshold voltage is approximately IV. It is being FIG. 2 is an equivalent circuit prepared to simply explain the operation of the memory cell shown in FIG. 1.

The emitter electrode 21 of the NPN transistor shown in FIG.
, a base electrode 22, and a collector electrode 27 are formed, respectively. A capacitor 24 shown in FIG. 2 is constituted by the conductor layer 13 shown in FIG. 1, the thin insulator layer 14, and the inversion layer formed on the surface of the P well. Digit line 23 and address line 25 correspond to conductor layer 13 and P-type buried layer 15 in FIG. 1, respectively. The potential distribution in the depth direction of the memory cell in FIG. 3 and FIG. 1 is shown as a, b during information storage, c, and
d, and are schematic diagrams shown at each time point e and f during writing.

In this figure, the N-type substrate 11 of FIG. , the thin insulator layer 14 corresponds to 34, respectively. For example, if we consider information storage with the N-type substrate fixed at 15V, the surface electrode at 15V, and the P-well at OV, the MIS diode constituting the memory cell in Figure 1 is Since it has a closing voltage of approximately IV, an inversion layer is formed on the surface of the P well.

When this inversion layer is empty, an empty inversion layer is formed as shown in FIG. 3a, and the potential of the inversion layer has a value close to 15V.
When the inversion layer is full of electrons, the electrons are localized on the P-well surface as shown in FIG. 3b, and the potential of the inversion layer becomes close to OV. In the memory cell of Figure 1, binary information is stored either when the inversion layer is empty or nearly empty, as in Figure 3a, or when the inversion layer is full or almost full of electrons, as in Figure 3b. It is memorized according to whether it is in a certain state or not.

The read operation is performed according to the following procedure.

First, all digit lines, that is, all front side electrodes 3
3 from 5V to 10V, connect them to the sense amplifier and leave them floating. At this time, the potential of the inversion layer of each memory cell is about 110V when the inversion layer is empty, and about 15V when it is full of electrons. Thereafter, a voltage of about 6V is applied to the address line connected to the memory cell to be read, as shown in FIG. 3c or d. In this case, since the voltage of the N-type substrate 31 is 5V, the portion of the N-type substrate other than the inversion layer and the P-well constitutes an NPN transistor as shown in FIG. 2, and the base electrode is in the forward direction. becomes biased. Therefore, electrons are injected from the N-type substrate, which is the emitter electrode, to the portion of the P well, which is the base electrode, other than the inversion layer. When the inversion layer is empty as shown in Figure 3a, electrons injected into the part of the P-well other than the inversion layer flow into the inversion layer as shown in Figure 3c, and the potential of the inversion layer increases to about 110V. It changes from to about 15V.

If the inversion layer is full of electrons as shown in Figure 3b,
As shown in FIG. 3d, the above-described flow of electrons does not occur, and the potential of the inversion layer remains at about 15 V and hardly changes. These potential changes in the inversion layer can be seen as changes in the collector electrode 27 in FIG. 2, and are transmitted to the sense amplifier through the capacitor 24 and digit line 23, and the binary information in the memory cell is read out.

These operations are performed in parallel for all memory cells connected to the address line to which about 6V is applied, so if you select only the contents of the memory cell to be read, the binary information in the memory cell to be read can be read. It means that it was done. Thereafter, the binary information lost from the memory cell during the current read is rewritten by performing the write operation described below, thereby completing the read operation.

The write operation is performed by the following procedure.

First, the read operation before rewriting is performed on the memory cell to which binary information is to be written and all memory cells connected to the same address line. As a result, the inversion layers of all memory cells connected to this address line are filled with electrons, and the binary information in those memory cells is temporarily stored in the sense amplifier. Next, the digit line connected to the memory cell whose inversion layer is to be emptied is set to 5V, the digit line connected to the memory cell whose inversion layer is to be filled with electrons is set to 10V, and the address line connected to the memory cell to be written is set to 5V. 5V}. In this way, the potential distribution of the memory cell whose inversion layer should be emptied becomes as shown in FIG. On the other hand, the potential distribution of the memory cell whose inversion layer should be filled with electrons is as shown in FIG. 3f, and the inversion layer remains filled with electrons. Thereafter, the address line connected to the memory cell to be written is set to 10 OV, and all the digit lines are rubbed at 15 V', resulting in the storage state shown in FIGS. 3a and 3b. By this write operation, the memory cell into which binary information is to be written is rewritten according to the information to be written. On the other hand, 2
Other memory cells connected to the same address line as the memory cell into which binary information is to be written are rewritten in accordance with the binary information read in the first half of this write operation. In a memory device, the contents of memory cells other than those on which read and write operations are performed must be preserved regardless of these operations.

In the case of the embodiment described above, the address lines connected to the memory cells on which no read/write operations are performed are as shown in FIG. 3a.
,b, it is saved in the OV.

On the other hand, the digit line has a potential of 110 V or 15 V, as shown in FIG. Therefore, in a memory cell where no read/write operations are performed, the potential difference between the gate electrode and the P well is maintained at 5V or more even under the worst conditions, so the contents of the memory cell, that is, the state of the inversion layer, are not affected by read/write operations. do not have. The digit line may be in a floating state during a read operation, but even at this time the digit line is floating at a value close to 10V, so the voltage does not drop below 5V. In the structure of the present invention, as can be seen from the above-mentioned embodiment (Fig. 1), the area per memory cell is determined only by the MIS structure diode for charge storage and the insulating region, so that It is possible to accumulate a large number of them.

Therefore, higher density can be achieved more easily than in memory cells with a conventional structure. When the structure of the present invention is used, a normal MIS transistor can be easily formed on the same chip as a memory cell, and therefore peripheral circuits can be easily integrated together with the memory cell.

As mentioned above, in order to explain the structure of the present invention and its operating principle, using an example of implementation whose main structure is shown in FIG. 0, 5, and 10V were used as shown.

However, the embodiments of the present invention are not limited to these examples, and there are naturally variations in the structure of the memory cell, and M
The threshold voltage and operating voltage of the IS diode are also not limited to these. Other structures, conductivity, and other voltage combinations are possible. For example, regarding the voltages of 0, 5, and 10V used in the above embodiment, they are all 15V while maintaining their mutual potential difference.
There is no problem even if you shift the voltage by -5, 0, or 15 V' and rub it. FIG. 4 is a sectional view showing the structure of a memory cell portion in another embodiment of the present invention.

This embodiment includes an N-type semiconductor substrate 41, a P well 42 formed on the surface of the semiconductor substrate, and an M well 42 formed on the surface of the P well.
Conductor layer 4 constituting the surface side electrode of the IS structure diode
3. It is composed of a thin insulating layer 44 that realizes the MIS structure, and a field insulating layer 16 that forms an insulating isolation region.The embodiment of FIG. The difference is that the buried layer 15) in Figure 1, which attempts to lower the resistance of the lead wire to the line, is omitted, but it can be operated in exactly the same way as the embodiment in Figure 1. . Now, in the embodiment illustrated above, it is assumed that the first conductivity type is N type and the second conductivity type is P type.
It has been described as a type.

However, the opposite may also be true. Further, although diffusion has been shown as a means for forming the second conductivity type layer in a partial region of the surface of the first conductivity type semiconductor substrate, this also has to be diffusion, but it is not necessary.

For example, there is no problem with ion implantation, and if it is necessary, there is no problem with selective epitaxial method. The conductor also does not need to be a metal; for example, it may be a semiconductor with sufficient conductivity,
.

Semiconductors do not necessarily have to be simple substances like silicon, but can also be things like compound semiconductors.
To put it bluntly, there is no necessity for it to be an inorganic substance. Further, it is not necessary to specify its crystallinity. Of course, single crystals are useful, but polycrystals and amorphous materials are also effective. Insulators also have a wide range of choice.

For example, silicon oxide and silicon nitride are common and easy to use, but there is no need to stick to them. When Yamaichi Group V compound semiconductors are used, their native oxides are also useful.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of a memory cell portion in one embodiment of the present invention. This embodiment includes an N-type semiconductor substrate 11, a P-type diffusion layer 12 formed on the semiconductor substrate, and an MI formed on the surface of the P-type diffusion layer.
A conductive layer 13 which is the surface side electrode of the S structure diode and also serves as a digit line or a lead line to the digit line.
, a thin insulator layer 14 constituting the MIS structure, an address line formed continuously with the P-type diffusion layer 12 or a P-type buried layer 15 serving as a lead line to the address line, and a thick field forming an insulating isolation region. It is composed of an insulating film 16 and an inversion layer 17 formed on the surface of the P-type diffusion layer.
FIG. 2 is an equivalent circuit prepared to simply explain the operation of the memory cell shown in FIG.
2. The inversion layer formed on the P-type diffusion surface constitutes the emitter electrode 21, base electrode 22, and collector electrode 27 of the NPN transistor, and thus constitutes the capacitor 24 of the MIS structure diode. FIG. 3 is for explaining the operation of the memory cell shown in FIG. 1, and is a schematic diagram showing the potential distribution in the depth direction of the memory cell. FIG. 4 is a sectional view showing the structure of a memory cell according to another embodiment of the present invention. Oh figure, 2 figures, 3 figures, 4 figures

Claims (1)

[Claims] 1. A second conductivity type layer that also serves as an address line or a lead wire to the address line formed on a part of the surface of the first conductivity type semiconductor substrate, and a thin insulator formed on the surface of the integrated layer of the second conductivity type layer. What is claimed is: 1. A semiconductor integrated memory device comprising a conductor layer formed on the surface of the thin insulating layer and serving as a digit line or a lead wire to the digit line.