JPS6034856B2 - PLL synthesizer radio receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a PLL digital synthesizer type receiver, and more particularly to a PLL digital synthesizer type radio receiver capable of presetting a desired reception channel and automatically tuning the preset channel. Regarding.

Recently, radio receivers using this type of PLL digital synthesizer system have become increasingly popular.

By the way, in order to preset a desired reception channel in a PLL digital synthesizer type radio receiver, a storage device is required to store the desired reception channel, and this storage device uses semiconductor random access technology, which is widely used. Some use memory.

As is well known, a random access memory retains its memory contents (preset data) while energized (ON), but when the energization is interrupted, the memory contents disappear. Therefore, in order to always retain the contents of the above memory, it is necessary to keep the random access memory powered at all times.

There are two methods of supplying power to the access memory as shown below.

One method is to separate the power source for the random access memory and the power source for the radio receiver, and keep the power on at all times regardless of whether the power source for the radio receiver is turned off. The other one is that when the power of the radio receiver is turned on, it is powered by the power of this radio receiver, and when the power of the radio receiver is turned off, the power of the random access memory is switched to the battery. , this is a method of energizing with this battery. However, in the former method, the contents of the memory will be erased if there is a power outage.

Also, in the latter method, since the battery has a limited lifespan, there is the disadvantage that the contents of the memory disappear after this lifespan, similar to the former method. Therefore, in such a case, it is necessary to re-preset the desired reception channel.

Setting presets is time-consuming and troublesome, especially when there are a large number of channels. The present invention was made in view of this point, and provides a PLL that can extremely easily re-set the preset when the contents of the random access memory are erased due to reasons such as power outage or battery life.
To provide a digital synthesizer receiver.

In other words, the main point of the present invention is that when the preset contents are erased due to a power outage, etc., and you want to reset the preset again, the received frequency band is auto-swept with a one-touch button operation, the frequency data of the broadcasting station is stored in order, and the auto-preset is performed. The reason is that we have made it possible to do this.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a PLL digital synthesizer radio receiver showing one embodiment of the present invention.
In FIG. 1, 1 is an antenna, 2 is a high frequency amplifier, 3 is a frequency mixer, 4 is an intermediate frequency amplifier, 5 is a wave detector, and 6 is a stereo demodulator. 7 indicates a PLL circuit, which includes a reference signal oscillator 71 and a programmable counter 72.
a phase comparator 73 that compares the phases of the output signal (fo/N) of the counter and the oscillation signal (ra) of the oscillator to detect the phase difference, and obtains a DC voltage according to the concession phase difference; A low-pass filter 74 integrates and smoothes the output voltage of the comparator to obtain a continuous voltage component proportional to the phase difference, and the oscillation frequency (fo) is proportionally controlled in height by increasing or decreasing the output DC voltage of the low-pass filter. Controlled oscillation frequency (ra)
It is comprised of a programmable counter 72 and a voltage controlled oscillator 75 that leads the frequency mixer 3 to the frequency mixer 3.

Reference numeral 8 indicates a control circuit, which includes a register 81 storing contents (data) for determining the receiving frequency, an initial value setting circuit 82, and a random access memory 83.
, an IF offset correction circuit 84 , a maximum/minimum frequency comparison circuit 85 , a clock pulse generation circuit 86 , and a maximum frequency detection signal terminal 87 .

Since these are generally well known, detailed explanation thereof will be omitted. 9
indicates a switch group; 91 is a memory light switch; 9 is a memory light switch;
2 to 95 are memory channel switches, and 96 is an auto sweep up switch.

Now, if you turn on the memory write switch 91 and turn on the channel switches 92 to 95, the contents of the register 81 (received frequency data) will be transferred to the random access memory 83.
This presets the receiving channel.

Channel switch 92 after presetting the receiving channel
When ˜95 is turned on, the contents written in the memory 83 are read out and supplied to the register 81.

The contents supplied to the register 81 are supplied to the display device 3 through the BCD-7 segment decoder 20 and displayed on the display device, as well as to the IF offset correction circuit 84.
supplied to The offset correction circuit 84 functions to correct the input contents, and more specifically, to correct the difference between the reception frequency and the local oscillation frequency, that is, the value corresponding to the intermediate frequency (IF). The content corrected by the offset correction circuit 84 is the PLL
A programmable counter 72 of circuit 7 is supplied. The programmable counter 72 determines the N value of the frequency division ratio 1/N based on the input contents. This allows reception of channels corresponding to channel switches 92-95. Next, when the auto sweep up switch 96 is turned on, the clock pulse generation circuit 86 generates a clock pulse. This clock pulse is applied to the counter input of register 81 and the contents of register 81 are thereby controlled. That is, auto sweep is started. The contents of the register 81 are supplied to the IF offset correction circuit 84 and at the same time to the reception bandwidth detection circuit 85. The reception band limit detection circuit 85 detects whether the output contents of the resistor are at the lowest frequency and the highest frequency of the reception band and generates a control signal. When the output content reaches the highest frequency value, the reception band detection circuit 85 generates a control signal. This control signal is supplied to the pulse generation circuit 86 and stops the oscillation operation of the generation circuit 86. Reference numeral 10 denotes an auto-sweep stop signal generation circuit that detects a part of the received signal from the intermediate frequency amplifier 4 and detector 5 when tuned to a certain reception channel during auto-sweep, and outputs a signal to stop the pulse generation circuit 86.

The above is a description of a general PLL digital synthesizer tuner.

10 is a circuit showing an example of an auto preset programming means according to the present invention.

111-116 are auto sweep up switches 96,
Relay circuits 121 to 128, which are connected in parallel with the memory light switch 91 and memory channel switches 92 to 95 and function in the same way as each switch, represent trigger pulse generation circuits, and the circuits are configured to generate differential pulses as shown in FIG. 2, for example. Circuit 120a, rectifier circuit 120b, monostable multipipelator circuit 120c, differentiator circuit 120d, rectifier circuit 120e
, a monostable multipipulator circuit 120f in series.

The input/output timing chart of each circuit in FIG. 2 is as shown in FIG. 3. 131 has two input terminals e,
The shift register has four output terminals a, b, c, and d.When a reset signal is input to the input terminal e, the outputs of the four output terminals a, b, c, and d are All become 0, and the trigger pulse oscillation circuit 12 is connected to the input terminal f.
When the output signal of 7, that is, one pulse shown in FIG. It is something that is shifted to the right on a daily basis.

141, 142, 143 are OR gate circuits, 151 is A
The ND gate circuit 161 indicates an auto preset switch, the fixed terminal of which is connected to the initial value setting circuit 82 of the control circuit 8, and the movable terminal connected to one input terminal of the OR gate circuit 141 through the trigger pulse generation circuit 121. It is also connected to the input terminal e of the shift register 131.

Output terminals a'b, c, d of the shift register 131 are connected to memory channel relay circuits 113, 114, 11 through trigger pulse generation circuits 123, 124, 125, 126.
5,116. Also, output terminals a, b, c
is connected to the input terminal of the OR gate circuit 142 through relay circuits 123, 124, and 125. The output terminal of the OR gate circuit 142 is connected to one input terminal of the OR gate circuit I43. The other input terminal of the OR gate circuit 143 is connected to the maximum frequency detection signal terminal 87 of the control circuit 8 through the inverter circuit 151.
The output terminal is connected to the other input terminal of the OR gate circuit 141 through the trigger pulse generation circuit 128. O
The output terminal of the R gate circuit 141 is connected to the auto sweep up relay circuit 111. The input terminal of the trigger pulse generation circuit 122 is connected to the automatic sweep stop signal generation circuit 9, and the output terminal is connected to the input terminal f of the shift register 131 through the trigger pulse generation circuit 127, and is also connected to the memory write relay circuit 112. There is. In such a program circuit, auto preset switch 1
When 61 is turned on, the initial value setting circuit 82 of the control circuit 8 operates and outputs the initial value, that is, the content (data) indicating the lowest tuned wave number of the reception channel.

This output is set in register 81. Also, at this time, the shift register 131 is reset, and its output terminals a~
All outputs of d become 0. When the auto preset switch 161 is turned on, the signal shown in FIG. 3A is input to the input terminal of the trigger pulse generation circuit 121, and the pulse generation circuit outputs a pulse delayed by a certain period of time as shown in FIG. 3G. . This output pulse is input to the relay circuit 111 through the OR gate circuit 141, and the memory write relay circuit 111 is turned ON for a time corresponding to the pulse width. As a result, the control circuit 8 starts auto-sweeping from the lowest frequency to the highest frequency of the receiving band, similar to when the auto-sweep switch 96 is turned on. When a certain channel frequency is received during this auto-sweep, the auto-sweep stop signal generating circuit 9 generates an auto-sweep stop signal, and the control circuit 9 stops the auto-sweep using the auto-sweep stop signal. Further, at this time, the output signal of the auto-sweep stop signal generation circuit 9 is inputted to the trigger pulse generation circuit 122. Trigger pulse generating circuit 122 outputs the pulse shown in FIG. 3G in response to its input, and this output pulse is input to memory write relay circuit 111, which turns on the relay circuit for a time corresponding to the pulse width. Further, the output pulse of the trigger pulse generation circuit 122 is inputted to the input terminal f of the shift register 31 through the trigger pulse generation circuit 127. Then, the shift register 131 outputs a signal of 1 to its output terminal a. This signal is input to the memory channel relay circuit 113 and turns on the relay circuit. This turns on the memory light switch 91 and turns on the memory channel switch 921.
It is the same as when you turn ○N. Therefore, the contents of register 81 are written to memory 83 at this time. Further, the output signal of the pulse generation circuit 123 is output from the OR gate circuits 142 and 14.
3 to the trigger pulse generation circuit 128.
The pulse generation circuit 128 outputs the pulse shown in FIG.
1 to the auto-sweep-up relay circuit 111, and the relay circuit 111 turns OFF for the time corresponding to the pulse width.
Do N. This will start autosweep again.
Thereafter, the above operation is repeated until the tuning frequency reaches the highest frequency, or when all channels have been written to the memory 83, the input/output relationships of the OR gate circuit 142, inverter circuit 151, and OR gate circuit 143 are shown in Table 1. The auto preset will end as shown below.

Although the auto preset switch 161 is not shown here, if it is linked with the power switch, there is no need to keep the memory 83 energized all the time. FIG. 4 is a block diagram showing another embodiment of the present invention in which the control circuit 8 and program means 100 in FIG. 1 are implemented by a microcomputer. In FIG. 4, 200 is a microcomputer (hereinafter referred to as a microcomputer) equipped with a random access memory, a read-only memory, and an input/output latch;
210 is an input keyboard of the microcomputer 200 configured in a matrix. The rest is the same as in Figure 1, so
Circuits that are the same as those in the figures are given the same numbers and their explanations will be omitted. The microcomputer 200 is programmed as shown in FIG. That is, FIG. 5a shows the main program. 5th below
The program shown in Figure a will be explained. In FIG. 5A, when the power is turned on to the microcomputer, initialization is first performed using a program 301. The contents of initialization include clearing the flag timer and other memories to 0, setting initial values, and displaying a power outage. Next, a program 302 creates display data, and a next program 303 displays the contents of the display data (dynamic lighting) and performs key input scanning. Next, a program 304 performs chattering of the data input by key input scanning and determines whether the data is valid. Next, program 305 determines the type of key input, flags, etc., and executes the next program 306.
-309 control is determined. 306 is a program that performs the auto sweep function, 307 is a program that performs the memory write function, 308 is a program that performs the memory channel function, and 309 is a program that performs the auto preset function. Details of these programs are as follows. It is shown in FIGS. 6 to 10.

When the above processing is completed, control is transferred to program 302, and the above operations are repeated. FIG. 5b shows an interrupt processing program, which uses a clock pulse of a commercial frequency (50/60 days 2) to generate an interrupt and count a timer used to perform an auto sweep, for example, one step sweep every 10 hsec. I do. If a numerical value is set in the timer, the program 311 decrements (subtracts by 1) and continues processing until the timer reaches 0. For example, if a clock of 50 Hz is used, an interrupt will occur every 2 hsec, and the contents of the timer will be decremented by 1 every 2 hsec. In order to use a 10hsec timer, it is sufficient to set it to 5.

Figure 6 shows the automatic shift up.

The program shown in FIG. 6 will be explained below. In FIG. 6, at the time of auto-sweep, a program 310 first sets an auto-sweep up flag (hereinafter referred to as the AS flag). This AS flag is maintained from program 305 to program 306 even after the autosweep key is released.
This is necessary to transfer control to the Next, a program 311 judges whether the timer is 0 (it is 0 when the key is pressed for the first time), and if the timer is 0, the program moves to the next program 312. Program 312 adds 1 to the PLL value, that is, the frequency division (N value) of the PLL programmable counter (value to step to the next station), and program 3
At step 13, the data is output to the PLL. After that, the program 314 receives the broadcast and determines whether or not a signal to stop auto-sweep has been input to the microcomputer, and if a stop signal has been input, the process moves to the next program 317.
Program 3 1 7 resets the AS flag and ends the auto sweep operation. If there is no stop signal in the program 314, the program moves to the program 315.
In step 15, it is determined whether the PLL value is the maximum value, and if it is the maximum value, the program moves to the next program 316, in which the PLL value is set to the minimum value. If it is not the maximum value in program 315, the program moves to program 318 and sets the timer (if it is a 10 hsec timer with a 50Hz clock, input 5). Thereafter, the process returns to the program 302 of FIG. 5a through . Unless another key is pressed, program 305 checks the AS flag and control passes to program 306. If the timer is 0, the process returns to the program 302 again through ①, and if the timer becomes 0, the process moves to the program 312 and further increments the PLL value by 1. In this manner, the auto sweep continues until a stop signal is received. FIG. 7 is a diagram showing the sweep, in which the axis is time and the vertical axis is the PLL value. FIG. 8 shows a memory write program. During memory write, a memory write flag (hereinafter referred to as MW flag) is set in program 319. Figure 9 shows the memory channel. program, and the program is actually channel 1, channel 2, channel 3...
It corresponds to keys such as... There are two types of memory channel functions: a function to write random access memo data, and a function to read the contents of random access memory. That is, in the case of a memory channel, control is transferred to the program 3201, which determines whether or not there is a MW flag, and if there is, the program 321 performs a memory write, and the program 322 resets the MW flag, and through (2) Return to program 302 of a.
If there is no such program, the program moves to program 323, in which data is IJ-coded from the random access memory and output to the PLL to receive the desired broadcast station.

FIG. 10 is an auto preset program of the present invention.

The program shown in FIG. 10 will be explained below. The auto preset program consists of auto sweep memory write and memory channels. 10th
In the figure, when control is transferred to program 324, this program determines whether a memory channel counter (hereinafter referred to as MC counter) is 0 or not. If it is 0 (initially it is 0), the next program 325 sets the auto preset flag (hereinafter referred to as the AP flag), the next program 326 sets the MC counter to 1, and the next program 327 initializes the PLL. Set to value.
This is the initialization of auto preset.
Next, enter program 331 after going through programs 328 and 329 with NO, and from here on, it is almost the same as the auto sweep program described above, but when a stop signal is input, the current PLL value is entered in programs 335 and 336. Random access memo written by Kawako. The random access memory channel is set to the same number as the MC power counter. After writing, the program 327 counts the MC counter to 11, the program 338 sets the auto-sweep timer, and returns to the program 302 in FIG. 5a through step 3. At this time, the AP flag is set, so the program goes to program 324 again, and this time it jumps to program 328. In programs 328 and 329, when the PLL reaches its maximum value or the number of prepared channels is full, the program moves to 33, and the program resets the AP flag and clears the MC counter to 0, and performs auto preset operation. stop. As can be seen from the above, according to the present invention, when the preset contents of the random access memory are erased due to a power outage or the like, the preset contents can be easily re-preset, which is very convenient.

Furthermore, if the auto preset switch is linked with the power switch, there is no need to keep the random access memo IJ' normally on all the time.

Furthermore, if a microcomputer is used for the control circuit and programming means, the circuit configuration can be simplified.

Further, according to the present invention, auto sweep ends when the number of memories prepared is preset, so if there are more receiving stations than the number of memories, specify the maximum channel after auto preset and further auto sweep from there. By doing so, you can easily find out which stations you were unable to write a memo to.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a trigger pulse generation circuit of the present invention, FIG. 3 is a timing chart thereof, and FIG. 4 is a block diagram showing an example of a trigger pulse generation circuit of the present invention. FIGS. 5 to 10 are block diagrams showing an embodiment, and are diagrams for explaining the contents of the microcomputer of the present invention. FIG. Figure 5b shows the interrupt timer processing program, Figure 6 shows the auto-sweep program, and Figure 7 shows the auto-sweep time versus PL.
Characteristic diagram showing the relationship with L value, Figure 8 is a memory write program, Figure 9 is a memory channel program, Figure 10 is
The figure shows an auto preset program. 8... Control circuit, 81... Regis evening,
83...Random access memory, 9""" switch group, 100...Program means, 111-116
...Relay circuit, 121-128...Trigger pulse generation circuit, 131...Shift register, 141-143...OR gate circuit, 151...Inverter circuit, 161... ...Auto preset switch, 200...Microcomputer, 210...Keyboard. Go 2 figures, 6 figures, 8 figures, 3 figures, 4 figures, S box figures? Figure O'0 figure

Claims (1)

[Claims] 1. A PLL synthesizer radio receiver equipped with a receive channel preset random access memory and an auto-sweep mechanism, including an auto-preset switch;
Program means is provided to control the auto sweep mechanism and automatically preset the reception channels in the memory in sequence when the switch is turned on, and the program means turns on the auto sweep mechanism when the auto preset switch is turned on. and a device for starting auto-sweep from the lowest frequency to the highest frequency of the receiving band or vice versa, and a device that detects when a certain channel frequency is received during auto-sweep and turns off the auto-sweep mechanism. A device for temporarily stopping the auto sweep, a device for presetting the reception channel at this time in memory, a device for turning on the auto sweep mechanism again after the presetting and starting the auto sweep, A device for detecting when the frequency reaches the highest frequency or the lowest frequency or when all data has been written to a prepared preset memory and turning off the auto sweep mechanism to completely stop the auto sweep. P characterized by being composed of
LL synthesizer radio receiver. 2 The programming means turns the auto preset switch on.
When it is N, the auto sweep mechanism is turned on and auto sweep is started from the lowest frequency of the reception band to the highest frequency or vice versa, and when a certain channel frequency is received during auto sweep, the auto sweep mechanism is turned off.
At this time, the auto sweep is temporarily stopped, the receive channel is preset in the memory, and after presetting, the above auto sweep mechanism is turned on again to start the auto sweep, and when the sweep frequency reaches the highest frequency or the lowest frequency, or Claims characterized in that the microcomputer has the function of detecting when all data has been written to the prepared preset memory and turning off the auto-sweep mechanism to completely stop the automatic tuning. The PLL synthesizer radio receiver according to item 1. 3. The PLL synthesizer radio receiver according to claim 1 or 2, wherein the auto preset switch is interlocked with a power switch.