JPS6036107B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-density, high-performance semiconductor memory device using MOS transistors as constituent elements.

As a conventionally known semiconductor memory device using MOS transistors, there is a dynamic RAM in which one MOS transistor Q and one capacitor C constitute one memory cell, as shown in FIG. This memory cell is “1” depending on the amount of charge accumulated in the capacitor C.
This memory cell is suitable for high integration because it has a small number of constituent elements, but the following problems arise with high integration.
A large number of memory cells will be connected to the bit line BL, and therefore the stray capacitance of the bit line BL will become larger than the capacitor C.
The value is extremely large compared to the capacity of . Then, the change in the potential of the bit line BL when the MOS transistor Q is made conductive when issuing a proposal is proportional to the charge of the capacitor C and inversely proportional to the stray capacitance of the bit line BL, so it becomes an extremely small value. . For this reason, even if a high-performance sense amplifier is used, it becomes difficult to correctly read out stored information to the outside. Furthermore, a memory cell as shown in FIG. 2 using three MOS transistors Q, .about.Q is known.

This is to set the connection point between the source of transistor Q and the gate of transistor Q2 as the information storage node N, and by making transistor Q conductive and applying a predetermined potential to the information storage node N' from bit line BL2. Writing is performed. The setting operation is to determine whether or not the precharged bit line BL is discharged via the MOS transistor Q2 according to the stored information when the word line WL conducts the MOS transistor Q3. This is done by being judged. In this memory cell,
Even if the stray capacitance of the bit line BL is large, the output signal will not become smaller due to capacitance division, unlike the memory cell shown in FIG.

Further, in the case of this memory cell, the stored information is not destroyed or changed by the issuing operation, and there is an advantage that non-destructive issuing can be performed. However, as is clear from the memory cell shown in Figure 1, it uses a large number of elements, and requires two word lines and two bit lines, so the area occupied by each memory cell is large, and it is also highly integrated. The problem is that it does not pass through the process. The present invention has been made in view of the above points, and it is an object of the present invention to provide a semiconductor memory device with high integration and high performance achieved by a novel memory cell structure using two MOS transistors.

FIG. 3 is an equivalent circuit of an embodiment of the present invention, showing one memory cell portion of a memory cell array arranged in a matrix on a semiconductor substrate.

The memory cell includes first MOS transistors Q, . and a second MOS transistor Q,2 having two layers of gate electrodes, and a first MOS transistor Q, . source and the second MOS transistor Q
, 2 are connected to each other, and this connection portion is used as an information storage node N. BL, BL are the first and second bit lines selected by the address in the column direction, WL, .
WL2 is the first and second word lines selected by the address in the row direction, and the first MOS transistors Q, .
Its gate electrode is connected to the first word line WL, and its drain is connected to the first bit line BL, respectively, and the second M
The second layer gate electrode of the OS transistor Q,2 is connected to the second word line WL2, the drain is connected to the second bit line BL2,
Each source is connected to power supply B. Second MOS
For example, if the transistor Q,2 is an n-channel structure,
As shown in FIG. 2, a first layer gate electrode 3 is provided on a p-type SJ substrate 1 with an insulating film 2 such as a silicon oxide film interposed therebetween, and a second layer gate electrode 3 is further provided on the p-type SJ substrate 1 with an insulating film 22 interposed therebetween. Gate electrode 3
2, and an n+ type drain 4 and source 5.

Such a structure can be easily formed by using polycrystalline silicon films as the first and second gate electrodes, for example. The operation of the memory configured in this way will be explained next using FIG. 5.

Transistor Q, . , Q, and 2 are both n-channel in this case, and the power supply B is at a low potential, for example, OV.
First, in the memory retention state, the first and second word lines WL,,W
Both L2 are at low potential. When writing “1” (high potential) to a memory cell, the first and second word lines WL
, , WL2 are both raised to a high potential, and the first bit line BL is raised to a high potential as data to be written into the memory cell. This makes the first MOS transistors Q, .
Node N is set to a high potential via , and "1" is written. At this time, if the second bit line BL2 is kept at a low potential, no current flows even if the second MOS transistors Q and 2 are conductive, and there is no wasted power consumption. Then, the first word line WL, is lowered to a low potential, and then the second word line WL2 is lowered to a low potential.
By lowering the potential to a low potential, the stored information "1" is confined to the node N'. At this time, the second MOS transistor Q
．． Due to the capacitive coupling between the first layer gate electrode and the second layer gate electrode of the bit lines BL. The voltage is lowered to the potential Vo, which is between the high potential and the low potential applied to the voltage. If the threshold voltage of the second MOS transistor Q,2 is set so that it does not conduct at the gate voltage yo, the potential of the second bit line BL will decrease unless the second word line WL2 is raised to a high voltage. Even if the current changes, the second MOS transistor Q,2 remains non-conductive. Memory information “0”
In order to write "(low potential), it is sufficient to apply a low potential to the first bit line BL, by the same operation as above. At this time, the second bit line BL2 is connected to the second MOS transistor. Since there is no conduction, there is no need to lower the potential to a low level.First
, if the second word lines WL, , WL2 are returned to a low potential, the capacitive coupling causes the node N to become a potential V lower than the written potential of the first bit line BL, similar to the previous "1" write. , and "0" is trapped. At this time, the first MOS transistors Q, . Care must be taken to prevent conduction or forward bias between the node N and the substrate. A read operation is performed by setting the second word line WL2 to a high potential.

When the second word line WL2 is set to a high potential, the potential of the node N returns to the potential at the time of writing.
MOS transistor Q,2 is conductive, and remains non-conductive if it is "0". Therefore, if the second bid line BL is precharged to a high potential and made floating,
When it is ``1'', the second bit line BL has a charge of the second M
It is discharged through the OS transistor and shows a potential drop,
When it is "0", there is no potential change. By reading this with a sense amplifier, it is possible to determine whether it is "1" or "0". This reading is non-destructive, and by returning the second word line WL2 to a low potential, the original storage state is reproduced. In addition,
If the capacitance between the gate electrodes of the second MOS transistors Q and 2, that is, the capacitance between the node N and the second word line WL2, is not appropriate, it may be useful to add an external adjustment capacitor. be. According to this embodiment, the information “
1” and “0”, the second MOS transistor Q,
Since reading is performed by determining conduction or non-conduction of 2,
Unlike the memory cell shown in Figure 1, the output signal level does not decrease with higher integration, and compared to the memory cell shown in Figure 2, which has the same operating principle, the number of components is smaller, and therefore the higher the integration It is easy to convert.

Furthermore, as is clear from the operation description, since no DC current flows, a memory with low power consumption can be realized. Furthermore, for the same reason, it is possible to choose a large conductance for each element, and by increasing the density, stray capacitance can be reduced to 4
・High-speed operation can be achieved because it can be made smaller. In terms of manufacturing technology, the two-layer gate electrode structure can be easily realized using the already established silicon gate process.
In the embodiment shown in FIG. 3, two bit lines BL and BL2 are used, but these are connected to a common bit line B as shown in FIG.
It can be summarized in L.

FIG. 7 shows the state of each node potential when the power supply B is operated at a high potential in this embodiment. “1” or “0”
” to the memory cell, the first and second word lines W
L, , WL2 are raised to a high potential, and a high potential or a low potential is applied to the bit line BL in accordance with the information to be written. Then, by lowering the potential of the first word line WL, and then lowering the potential of the second word line WL2, the potential of the first word line WL,
”, “0”, the potentials Vo, V, are confined at the node N. Even in this write operation, no direct current flows through the second MOS transistor Q,2. This is done by applying a high potential. “1”
, the second MOS transistor Q,2 becomes conductive or non-conductive depending on “0”, so if the bit line BL is precharged to a low potential and made floating, “1”
”, the potential of the bit line BL rises due to the current from the power supply B, and when it is “1”, there is no change in the potential of the bit line BL. This potential change is detected by a sense amplifier and the potential is changed to “1” or “0”.
8 is an embodiment in which the first and second word lines WL, , WL in the embodiment of FIG. 3 are combined as a common word line WL.

In this embodiment, for example, the power supply B is set to a low potential, and the common word line WL is operated by applying different potentials during writing and when issuing. FIG. 9 shows potential changes at each node. For information writing, the first high potential V2 is applied to the word line WL, and the first MOS transistors Q, . “
1", the first bit line BL is set to a high potential and the second bit line BL2 is set to a low potential; for "0", the reverse is done,
A predetermined potential is written to node N. Read information 'well, 2nd
After precharging the bit line BL2 to a high potential and making it floating, the word line WL is set to the first high voltage V2.
A lower second high potential V3 is set. First MOS transistor Q. ．． If you choose the threshold value between V2 and V3,
At this time, the first MOS transistor Q,, is not conductive,
Information is not destroyed. At this time, due to the rise in the potential of the word line WL, the potential of the node N is "1", V4, "
0", it is raised to V5, but if the threshold value of the second MOS transistor Q12 is selected between V4 and V5,
The second MOS transistor Q,2 is conductive at “1” and “0”
”, it becomes non-conductive.Therefore, “1” and “0” are determined by the potential change of the second bit line BL.FIG. 10 further shows that the first and second bit lines BL, BL2 This is an embodiment in which the first and second word lines WL, , WL2 are combined as a common word line WL at the same time as the common bit line BL.

In this embodiment, for example, the power supply B is set to a high potential, and writing and reading are performed as follows. The potential change of each node is
Shown in Figure 1. First, information writing is performed by setting the word line WL to the first high potential V2 and writing the bit line BL as in the embodiment shown in FIG.
This is done by applying a high potential or a low potential to match the information “1” or “0”. To output information, the bit line BL is precharged to a low potential, then set to a floating state, and the word line WL is set to a second high potential V lower than the first high potential.
Set it to 3. In this case as well, the first MOS transistors Q, .
Destruction of stored information can be prevented by selecting the threshold between V2 and V3. At this time, the potential of node N is V4 if it is "1", and V5 if it is "0".
However, as in the previous embodiment, the second M
By selecting the threshold values of OS transistors Q and 2 between V4 and V5, the second MO
The S transistors Q and 2 become conductive and non-conductive, and the potential of the precharged bit line BL changes to "1" or ".
0" is read out. It is clear that the embodiments shown in FIGS. 6, 8, and 10 described above can also provide the same effect as the embodiment shown in FIG. 3.

In the embodiments shown in FIGS. 6, 8, and 10, the potential relationships are more complicated than in FIG. 3, and restrictions on element characteristics are greater, but by sharing signal lines, higher integration can be achieved. becomes possible. Note that the operation mode of each memory cell described above is just an example, and various modifications can be made in, for example, how to select the potential of the power supply B and the bit line.

Furthermore, the MOS transistor Q,2 having a two-layer gate electrode structure is not limited to that shown in FIG.
A structure in which the second layer gate electrode 32 is provided to cover the first layer gate electrode 3 as shown in FIG. 13 can be selected depending on the required characteristics. Further, in the above embodiments, the case where the MOS transistors are n-channel has been described, but both may be p-channel, or one may be n-channel and the other may be p-channel. As described above, according to the present invention, it is possible to achieve higher integration and higher performance of a MOS type memory device by using a novel memory cell structure using two MOS transistors.

[Brief explanation of drawings]

1 and 2 are equivalent circuit diagrams showing an example of the configuration of a conventional memory cell, FIG. 3 is an equivalent circuit diagram showing the configuration of a memory cell according to an embodiment of the present invention, and FIG. A schematic cross-sectional view of a MOS transistor used in a memory cell, FIG. 5 is an explanatory diagram of the operation of the memory cell in FIG. 3, FIG. 6 is an equivalent circuit diagram showing the configuration of a memory cell in another embodiment, and FIG. 8 is an equivalent circuit diagram showing the structure of a memory cell of another embodiment, FIG. 9 is an explanatory diagram of its operation, and FIG.
The figure is an equivalent circuit diagram showing the structure of a memo IJ cell of another embodiment, FIG. 11 is an explanatory diagram of its operation, and FIGS. 12 and 13 are schematic diagrams showing other structural examples of MOS transistors used in the memory cell. FIG. Q,,...,. ．． First MOS transistor, Q, 2...
... MOS transistor of younger brother 2, N ... information storage node, BL,, BL, BL ... bit line, WL
, WL, WL... Word line, B... Power supply,
1... p-type Si substrate, 2,, 22... insulating film, 3,... first layer gate electrode, 32... second layer
Layer gate electrode, 4...drain, 5...source. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 10 Figure 9 Figure 11 Figure 12 Figure 13

Claims (1)

[Claims] 1. A first MOS transistor and a second MOS transistor having two layers of gate electrodes are integrated, and the first MOS transistor
A memory cell is configured by connecting the source of the S transistor and the first layer gate electrode of the second MOS transistor and using this connection as an information storage node, and
Predetermined information is written into the information storage node by making the transistor conductive and applying a predetermined potential to its drain, and by applying a predetermined potential to the second layer gate electrode of the second MOS transistor, the second MOS transistor is written. 1. A semiconductor memory device characterized in that information is read based on the degree of conductivity of the semiconductor memory device. 2 The gate electrode of the first MOS transistor is connected to the first word line, the drain is connected to the first bit line, and the second layer gate electrode of the second MOS transistor is connected to the second word line.
2. The semiconductor memory device according to claim 1, wherein the memory cells are arranged in a matrix, with the drain connected to the second bit line, and the source connected to a predetermined power supply. 3. The semiconductor memory device according to claim 2, wherein the first bit line and the second bit line are a common bit line. 4. The semiconductor memory device according to claim 2, wherein the first word line and the second word line are a common word line.