JPS6036141B2 - Frame synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frame synchronization circuit for preventing erroneous synchronization due to a pseudo synchronization pattern of a PCMI next group frame.

In the PCMI next group of frames, the basic frame pattern (1,
0, 1, 0, 1, 0) and multi-frame patterns (0,
0, 1, 1, 1, *) are alternately allocated one frame at a time, and 12 basic frames constitute one multiframe.

The basic frame pattern is for frame synchronization by repeating "1" and "0", while the multi-frame pattern is for example "0", "0", "1", "1",
By repeating “1” and “*”, “*” is used for specific information, such as fault indication information, and the signal receiving station uses “*”
The arrival of the pattern (0, 0, 1, 1, 1) preceding `` identifies that the failure display information will arrive after that, and if the arriving ``*'' is ``0'', it is normal. 1
”, this allows the receiving station to know that there is some sort of problem on the line on the other side.

Therefore, in the PCMI next group of frames, it is necessary not only to have frame synchronization, but also to have synchronization with respect to the multi-frame pattern. When synchronizing such PCMI next groups, since the basic frame pattern has a smaller number of repeated bits than the multi-frame pattern, a pseudo basic frame pattern is likely to be included in the data signal. Conventionally, when this pseudo basic frame pattern is detected, This has the disadvantage that basic frame synchronization is established in a pseudo manner.

The present invention eliminates such drawbacks and provides a frame synchronization circuit that does not perform synchronization pull-in.

A detailed explanation will be given below with reference to the drawings.

Figure 1 is a diagram showing the frame structure of a general PCMI next group.As shown in c, 8 bits D, ~D8 constitute one channel, and this is divided into 24 channels 1~24, and an S bit (
1 bit) to constitute one frame (basic frame), and F, to F, 2 basic frames constitute a multiframe.

Here, basic frame patterns and multi-frame patterns are alternately written in the S bits shown in b, and their arrangement is 10001101110* as shown in a.

In this case, the basic frame pattern is written in odd-numbered frames and the multi-frame pattern is written in even-numbered frames, so the basic frame pattern is 101010.
, the multi-frame pattern is 00111*. Second
The figure shows a conventional frame synchronization circuit, in which 11 is a received data input terminal, 12 is a basic frame pattern detection circuit, 13 is a multi-frame pattern detection circuit, 14 is a synchronization protection circuit, 15 is a frame synchronization counter, 16 is an and gate. To explain the operation of this frame synchronization circuit, when received data arrives at the input terminal 11, the basic frame pattern detection circuit 12 and the multiframe pattern detection circuit 13 monitor the incoming signal every other frame.

However, the phase of the signals monitored by the basic frame pattern detection circuit 12 and the multi-frame pattern detection circuit 13 is 1.
The frame is misaligned.

In the basic frame pattern detection circuit 12, the incoming signal matches the inverted logic of the signal two frames before, that is, 0.
．． 1 repeat pattern or not, and if they do not match, an error pulse EP is sent out. On the other hand, the multi-frame pattern detection circuit 13 detects a predetermined pattern 001.
11 is generated, and the matching with the incoming signal is monitored sequentially from the beginning of this pattern, and if there is a mismatch, an error pulse E is generated.
Send P2. Therefore, since both error pulses EP and EP2 are sent out when synchronization is not established, the outputs PR and EP of the synchronization protection circuit 14 based on EP2,
The shift pulse is determined by the logical product of frame synchronization counter 1.
5, the frame synchronization counter 15 shifts by 1 bit, and the phases of the signals monitored by the basic frame pattern detection circuit 12 and the multiframe pattern detection circuit 13 each advance by 1 bit. In this way, the phase of the monitoring signal is sequentially shifted one bit at a time until synchronization is established. FIG. 3 shows the state of this synchronization, where DA is the received data, EP, EP2, PR, and SP are the error pulses 1 and 2 in FIG. 2, the output of the synchronization protection circuit, and the shift pulse, respectively.

Therefore, when the received data DA arrives and synchronization starts, since synchronization is not established at first, eff pulses EP and EP2 are generated, synchronization starts, and after a predetermined forward protection time elapses, synchronization protection is applied. A shift pulse SP is sent to the frame synchronization counter 5 by the AND of the output PR of the circuit 14 and the error pulse EP, and the phase of the monitoring signal is sequentially shifted. When synchronization with the basic frame pattern is achieved in this way, At that point, the error pulse EP,
On the other hand, once synchronization with the basic frame pattern is achieved, synchronization with the multi-frame pattern is achieved after a certain period of time and complete synchronization is achieved.

Incidentally, the output PR of the synchronization protection circuit 14 is stopped from being transmitted after a predetermined backward protection time has elapsed. In such a conventional frame synchronization circuit, when a pseudo basic frame pattern arrives, the transmission of the eff pulse EP, stops and the shift pulse SP is no longer transmitted, so that the frame synchronization counter 1
It becomes impossible to shift 5 bit by bit and shift to the hunting state.

Specifically, for example, when the data terminal is not communicating data, the pattern 00111111 (fixed) sent as an idle signal from the data terminal is (612).
When considering an envelope configuration, the frames are arranged as shown in FIG. 4 on the PCMI next group frame. Bi in the diagram
t indicates a bit, and has an 8-bit configuration of D, to D8, and No. exemplified eight frames numbered 1 to 8. Further, F and S are added when the envelope is assembled, and F is an envelope frame bit and S is a status bit. If we pay attention to the D2 bit, a repetition of 0.1 appears every other frame as shown by the dashed line, which is the same as the basic frame pattern.

Therefore, when the basic frame pattern detection circuit detects such a pseudo basic frame pattern, the error pulse EP is no longer sent as described above, and the shift of the frame synchronization counter stops even though synchronization has not been established. Resulting in. The present invention solves these drawbacks and provides a frame synchronization circuit in which the shift of the frame synchronization counter does not stop even when a pseudo basic frame pattern is received.

Hereinafter, the present invention will be explained along with one embodiment thereof.

FIG. 5 is a diagram showing one embodiment of the frame synchronization circuit according to the present invention, in which the same numbers as in FIG. 2 indicate the same components as in FIG. The OR gate, EP3, is an error pulse. The synchronization state monitoring circuit 51 monitors the error pulses EP, , EP2 and the output PR of the synchronization protection circuit. is to output one pulse EP3 if EP2 and PR are still being output after a predetermined time has elapsed from the time of stopping.

Therefore, even if the pseudo basic frame pattern is detected by the basic frame pattern detection circuit 12 and the EP stops, the synchronization state monitoring circuit 51 starts counting time from the time when the EP stops, and after the predetermined time T has passed, the synchronization state monitoring circuit 51 still If EP2 and PR are being output, EP3 is output, and a shift pulse SP is output by ANDing it with PR at the gate 16 to shift the frame synchronization counter 15 by 1 bit, and hunting is performed again.

Thereafter, the frame synchronization counter 15 continues to shift until synchronization is established and both EP and PR are no longer output. FIG. 6 shows the state of synchronization by the frame synchronization circuit of the present invention, and similarly to FIG. 3, it shows the data DA and each output of the frame synchronization circuit.

When synchronization is started in the frame synchronization circuit and a pseudo basic frame pattern is detected, the EP stops.

At the same time, the SP that was being output together with the PR output is also stopped, and the shift of the frame synchronization counter is stopped. From this point on, the synchronization state monitoring circuit starts counting time.

In this case, synchronization is not established just by detecting the pseudo basic frame pattern, so EP2 and PR are continuously output. Therefore, when the synchronization state monitoring circuit counts the predetermined time T, EP2 and PR are output, so EP3 is output, and SP is output due to EP3 and PR, and the frame synchronization counter 15 becomes 1.
The bits are shifted and EP, is output again, so EP, and S
The output of SP is restarted by P. After that, if synchronization is established, even if EP, stops, EP2,P
Since R is stopped, EP3 is not output.

As described above, according to the present invention, even if a pseudo basic frame pattern is detected, the shift of the frame synchronization counter does not stop there and erroneous synchronization pull-in occurs, and the shift of the frame synchronization counter continues until synchronization is reliably established. A frame synchronization circuit is implemented.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the frame structure of a general PCMI next group,
Fig. 2 is a block diagram of a conventional frame synchronization circuit, Fig. 3 is a diagram showing the state of synchronization in the conventional frame synchronization circuit, Fig. 4 is a diagram showing an example of a received signal, and Fig. 5 is a diagram of the present invention. FIG. 6 is a block diagram showing an example of a frame synchronization circuit according to the present invention. In the figure, 12 is a basic frame pattern detection circuit; 13 is a basic frame pattern detection circuit;
is a multi-frame pattern frame synchronization circuit, 14 is a synchronization protection circuit, 15 is a frame synchronization counter, 51 is a synchronization state monitoring circuit, EP, EP2 and EP3 are error pulses, PR is the output of the synchronization protection circuit, and SP is a shift pulse. show. Fig. 4 Dancing crab Fig. 5

Claims (1)

[Claims] 1 A repetition inserted into a received signal at a predetermined period in a frame synchronization circuit that configures a multiframe with a predetermined number of basic frames and establishes a normal synchronization state when both basic frame synchronization and multiframe synchronization are established. After basic frame synchronization is established by searching for a basic frame pattern with n bits (n≧2), multi-frame synchronization is performed by searching for a multi-frame pattern with repeated bits m (m>n) inserted at predetermined intervals in the received signal. A frame synchronization circuit that monitors a synchronization pull-in state for a certain period of time, and when it cannot shift to a synchronization state, shifts a frame synchronization counter used for both synchronizations by one bit to perform rehunting.