JPS603711B2 - read-only storage - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a read-only memory device, and in particular, to a fixed mask read-only memory device (hereinafter referred to as ROM) that can achieve high density, it is intended to increase the capacity of memory cells. This is what I did.

In conventional semiconductor fixed mask ROMs, which consist of multiple insulated gate field effect transistors (hereinafter abbreviated as MISFETs), MISFETs are arranged extremely densely on a semiconductor substrate.
ET memory cells were arranged. FIG. 1 shows, as an example of a conventional fixed mask ROM, a MISFET ROM circuit having a complementary configuration of 2×2 bits. This first
101 and 102 in the figure are P-channel MISFETs
, 1 03, 1 05 are N-channel MISFETs, 1
06, 107 are address lines (A1, A2).

Further, 108 and 109 are bit lines (data read line B
1, B2). FIG. 2 shows a plan view (pattern diagram) of the memory cell portion in FIG. 1, and 201 and 202 in FIG. 2 are N-type high concentration diffusion layers (hereinafter referred to as N-type diffusion layers). , which is both a bit line and a drain region. Further, 203 is an N type diffusion layer, which is a ground line and also serves as a source region.

Insulators 204 to 206 are thinly formed, and the skin SF between the N-type diffusion layers 201 and 202 and the ground wire 203
It constitutes an ET, and its drain and source become conductive if a voltage equal to or higher than its threshold VT voltage is applied thereto. Further, 207 and 208 are metal wirings of address lines and gate electrodes.

Further, 209 is a P-type substrate region (in this case, a diffusion layer) of an N-channel MISFET. Here, the first explanation is
Returning to the diagram, the P-channel N rainbow SFET in Figure 1
The sources of 101 and 102 are connected to the power supply (voltage VDo), and the drains are connected to the bit lines 108 and 102, respectively.
09, and a precharge signal P is applied to its gate.

These MISFETIOI and 102 have “L” on the gate.
When a level (low voltage) is applied, it becomes conductive, and when an "H" level (high potential) is applied, it becomes non-conductive. N channel skin SFE
The gate of TI03 is connected to the address line 106, the drain side is connected to the bit line 108 (BI), and the source side is grounded.

Further, the gate of the N-channel MISFET I04 is connected to the address line 106, and the drain side is connected to the bit line 109.
The source side is also grounded. Furthermore, the gate of the N-channel MISFET I05 is connected to the address line 107, and the drain side is connected to the bit line 109.
and the source side is grounded. These N
The channel MISFETs I03 to 105 have “H” on their gates.
” level (high potential) is applied, conduction occurs, and “L” level (
When a low potential) is applied, it becomes non-conductive. Now, in order to operate the fixed mask ROM of FIG. 1 and read out the stored information, first, the address lines 106 and 107 are set to "L" level, and the N-channel MISFET of each memory cell is
Keep I03 to 105 non-conductive.

Next, the potential of the signal line JP applied to the gates of the P-channel MISFETIO1 and 102 is set to "L" level to conduct the bit lines 108 and 109, and the bit lines 108 and 109 are connected to the power supply voltage V.
.

Charge to level D (“1” level). After charging the bit lines 108 and 109, the potential of the signal line ◇P is set to the HJ level to make MISFETIO1 and 102 non-conductive.Next, select one of the address lines 106 and 107.
For example, by setting the address line 106 (AI) to "H" level, the N-channel MISFET I03
and 104 are brought into conduction, and the charges stored in the bit lines 108 and 109 are discharged to the ground through these MISFETs I03 and 104. As a result, bit line 108,1
09 becomes the ground level (“0” level), and the storage data (M of the memory cell) corresponding to the address line 106 (AI)
bit line 108 (corresponding to the presence or absence of ISFET)
), 109 (B2). Also,
When address line 1071 (A2) goes to "H" level,
Only N-channel MIS FETI 05 is conductive, bit line 108 (BI) is at “1” level, bit line 109
becomes the "0" level and outputs 4.

In this way, the MISF in the memory corresponding to the address line
Depending on the presence or absence of ET, a "1" or "0" level is output on the bit line, thereby making it possible to read stored data.

In this type of memory cell configuration, one MISFE
Only binary information (“1” and “0”) can be obtained depending on the presence or absence of T, and in order to achieve large capacity, M in the memory cell must be
It is necessary to reduce the size of the ISFET and each dimension, and there are many difficulties in terms of productivity, cost, and miniaturization.

This invention was made to eliminate the above-mentioned conventional drawbacks, and by storing information of two or more values in the skin SFET of one memory cell, it is possible to increase the capacity without reducing each dimension. It is an object of the present invention to provide a read-only storage device that can achieve this goal and is also advantageous in terms of productivity, cost, miniaturization, etc.

Embodiments of the read-only storage device of the present invention will be described below with reference to the drawings.

FIG. 3 is a circuit diagram showing the configuration of this embodiment. Prior to explaining the circuit configuration of FIG. I decided to do it. In order for the source and drain of the MISFET to become conductive, this is achieved by applying a voltage higher than the threshold value VT to the gate. is generally expressed as the following equation {1).

V'=? MS 12? F ten total QSS,. ．． 、． ．． [,) In this equation, Ms: gate metal-Si work function difference, ? F: Fermi level of substrate; tox: thickness of gate insulating film; ox: dielectric constant of gate insulating film; Qss: surface charge density.

As a method of changing the threshold value Vr from this {1' expression, there are the methods listed below.

'11 Method of changing the work function ◇ Ms of the gate electrode material (for example, A, Si, Mo, etc.), {2) Method of changing the thickness of the gate insulating film, [3' The yield rate of the insulating film (for example, SiQ, Si3N4
, A203, etc.), [41 Methods of changing the impurity concentration NA of the substrate (GF), ■ Methods of changing the number of surface states Nss (for example, changing the type of gate insulating film, changing the annealing conditions, etc.) be.

Here, taking as an example a method of changing the impurity concentration on the surface of the substrate using ion implantation, which has the advantages of easy voltage control, wide control range, and good reproducibility, P
The specific resistance of the mold substrate is 3 to 401 arc, the insulation film thickness is 1000 A, the threshold value VT is about IV, and the boron impurity to the substrate surface of the gate part is 3 to 4 × 1 bili.
ons/value after ion implantation, value VT
The change △VT is about 2V, and depending on the presence or absence of ion implantation, there are two types of M with Z threshold VT: IV and 3V.
Although an ISFET can be manufactured, in principle, it is possible to control the threshold value VT in infinite steps by changing the amount of ion implantation.

The read-only storage device of the present invention is constructed using MISFETs having different threshold values and VTZs as described above, and an embodiment of the present invention will be described below with reference to FIG. do.

Similar to FIG. 1, FIG. 3 illustrates a ROM consisting of two address lines and two bit lines.

In FIG. 3, 301 and 302 are P-channel MISFETs, and 303 to 305 are N-channel MISFET memory cells. MIS FET3
Among 0 3 to 3 0 5, the threshold value of MIS2FET 303 is VT, and the threshold value of MISFETs 304 and 305 is VT2. Further, 306 and 307 are address lines (AI, A2), respectively, and 308 and 3
09 are bit lines 308 and 309 (B1, B2) respectively
There are three. These MISFETs 301 to 305, address lines 306, 307, and bit lines 308, 309 have the same memory cell configuration, with the only difference being the reference numerals of each component, so explanations of their connections will be omitted here. do. 3 bit line 308 (BI
) and 309 (B2) are connected to 2-bit shift registers 310 and 311, respectively, and clock J is supplied to both 2-bit shift registers 310 and 311 through shift register clock wiring 314. It's on. Outputs are transferred from the output ends of the 2-bit shift registers 310 and 311 to binary decoders 315 and 316 through shift register output wirings 312 and 313.

Binary output wiring 317 (BI1, B12) and 318 are connected to the output ends of the binary decoders 315 and 316, respectively.
(B21, B22) are connected. Next, the operation of the read-only storage device of the present invention will be explained using the time chart of FIG. 4.

In the same way as in the case of FIG.
09, 2-bit shift registers 310, 311
In other words, it is inputted into . In the memory cell shown in FIG. 3, the N-channel MISFET 303
As shown in FIG. 4, the voltage levels of address lines 306 and 307 are 2 of VG, VG2 for the threshold value VT2 of MISFETs 304 and 305.
There are levels, and their relationships are as follows.

VG2>VT2>VG,>VT, ...[
2} In this case, MISFET30 with threshold value VT,
When the gate voltage of 3 becomes VG or VG2, this M
The ISFET 303 is conductive, while the MISFETs 304 and 305 having a threshold value VT2 are non-conductive even when their gate voltage reaches VG, and become conductive when the voltage reaches VG2.

Now, when the address lines 306 and 307 are at a low potential (a level at which no MISFET in the memory cell is conductive), "gate signals of P channel MISFETs 301 and 302?P(
(see FIG. 4) is at a high potential (MISFETs 301 and 302 are non-conductive).

Next, the gate voltage signal JP of the P-channel MISFETs 301 and 302 is set to a low potential, and the MISFET 30
MISFETs 301 and 302 are made conductive, the bit lines 308 and 309 are charged to the voltage Voo level of the power supply, and then the gate signal ◇P is made high potential to make these MISFETs 301 and 302 non-conductive. Next, a case will be considered in which memory information corresponding to one selected address line, for example address line 306 (AI), is read.

First, set the voltage level of address line 306 (AI) to Vc,
and 0ru. As a result, only the MISFET 303 becomes conductive, and the electric charge stored in the bit line 308 is removed from the MISFET 303.
Discharged to ground through FET 303 and bit line 30
81 becomes the "0" level, and the bit line 309 remains at the "1" level. At this time, “0” on the bit line 308
Each level of the “1” level of the bit line 309 is 2
A clock signal is applied to the bit shift registers 310 and 311 through the shift register clock wiring 314 as shown in FIG. With the first clock pulse of
311.

Next, if the level of the address wiring 306 is VG2,
MISFETs 303 and 304 in the memory cell become conductive,
The charge on bit line 309 is discharged to ground through MISFET 304. As a result, both bit lines 308, 30
9 are both at the "0" level. Both bit lines 308
, 309 is the second pulse of the clock signal ◇ in FIG.
1.

At this time, the 2-bit shift register 310' is "0,
0" data has been read, and 2.
This means that the bit shift register 311 has been loaded with data “1, 0”. In this way, it becomes possible to read out multi-level information from the memory corresponding to the voltages VG, VG2 of the address lines 306.

In addition, in order to convert the read data into binary code, the parallel output lines of each shift register 310, 311,
That is, shift register output wirings 312 and 313 are subjected to 2-bit binary conversion using binary decoders 315 and 316, and output to binary output wirings 317 and 318.

When address line 307 is selected, RO
M data can be read.

The input/output relationship of the binary decoders 315 and 316 is as shown in Table 1 below. <Table 1> The output (binary code) read corresponding to each address is as shown in Table 2 below.

<Table 2> As shown in this Table 2, the threshold value VT is VT,
, VT2 has two types of memory cells, one MISF
Three-value information can be obtained from ET.

As explained above, in the above embodiment, one MI
Three-value information “0,0”, “0,1”, “1,
0" can be obtained, so the binary information of the conventional memory cell "0" can be obtained.
, 1” from 1. Although we have shown an example in which needle sound information can be obtained, in practice, the threshold value V and level can be considered to be infinite.
By similarly creating the address line voltage for it,
There is an advantage that a lot of information can be read out from one MISFET memory cell.

For example, set n threshold values (VT. to VTn) and set the corresponding address voltage (gate voltage) to VG,
~VGn, if we create the relationship of the following '3} formula, Vcn
>VTn>VG(n-,)>VT(n-,)...>V
c,>VH...[3' MI where the amount of information in the memory cell is one
(n+1) can be obtained from SFET.

As detailed above, according to the read-only storage device of the present invention, information of two or more values can be obtained from the MISFET of one memory cell, so a large-capacity mask ROM can be realized without increasing the number of memory cells. It is extremely advantageous for increasing memory capacity.

Further, in the device of the present invention, which expresses information on each bit line as a combination of logical "1" and "0", everything can be constructed digitally, so it has the effect of simplifying the construction.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional fixed mask ROM, FIG. 2 is a plan view of a memory cell portion of the fixed mask ROM of FIG. 1, and FIG. 3 is a circuit diagram of an embodiment of a read-only memory device of the present invention. , FIG. 4 is a time chart for explaining the operation of the read-only storage device. 301 to 305... MISFETs 306, 307...
Address lines, 308, 309...Bit lines, 310, 31
1... 2-bit shift register, 312, 313... Shift register output wiring, 314... Clock for shift register, 315, 316... Binary decoder, 317
, 318...Binary output wiring. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1 A plurality of insulated gate field effect transistors are connected between each bit line and ground, have mutually different threshold values, and have gates connected to a common address line, and voltages of different levels are sequentially applied to the address lines. A means for applying voltage, a shift register into which logical "1" and "0" information of each bit line is input each time this voltage is applied, and a circuit that converts the information stored in this shift register into a binary code. A read-only storage device comprising: