JPS603715B2 - variable length shift register - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to digital shift registers, particularly variable length shift registers.

Conventionally, in order to construct a shift register that can specify an arbitrary shift amount, that is, a variable-length shift register, several types of shift registers with different shift amounts have been connected together. For example, specify the shift amount in binary from 0 to 1023.
In order to configure a variable length shift register that can be arbitrarily specified within the range of 512, 256, 12 & 64, 32,
IG 8, 4, 2, IBit shift registers, IBit shift registers and 1-bit multiplexer are required. FIG. 1 shows input data IBit according to the conventional method.
This is an example of a circuit of a variable length shift register in which the shift amount can be specified in one ship. Clock signal 300 is input to each shift register 29-20. Multiplexer (hereinafter referred to as MUX)
) 19 is 1 of the specified shift amount M signal 102
Input data signal 100 by M needle signal 209 of ship itth
or 51 selectively outputs the output of the IT shift register 29,
The MUX 18 is the M8 of the shift amount M signal 102.
The output of the MUXI 9 or the output of the 25 paper it shift register 28 is selectively outputted by the signal 2 (female). MU in the same way below
X17, 16,..., 11, 10 are shift amount M signals 10
8, 7, ..., 2, IBit M7, M6, ..., M of 2
1, MN signals 207, 206..., 201, 200 cause the output of MUXI & 17,..., 12, 11 to become 12 spots i
t shift register 27, 64-bit shift register 26
, . . . select the outputs of the IT shift register 21 and the IBit shift register 20. The number of ICs required for the circuit configuration of FIG. 1 is determined by simple calculation, and it is determined that 1 or more ICs are required. With the circuit configuration shown in Figure 1, multiple Bi
t, for example, to configure a variable length shift register for processing ship IT, eight sets of circuits are required, and the number of ICs is 80 or more. Furthermore, if a two-dimensional shift register, which is often used in preprocessing circuits for image processing, etc., is constructed as a variable length shift register, a very large number of ICs will be required. For example, if the input data is paper IT and the size of the two-dimensional shift register is a maximum of 102 boxes x 8 columns, the number of ICs in the circuit configuration shown in FIG. 1 will be 10 x 8 x 8 = 64. The main drawback of this large amount of shift registers is the use of several types of shift registers with different shift amounts. An object of the present invention is to provide a variable length shift register with a simple circuit configuration without using many types of shift registers with different shift amounts. An object of the present invention is to provide a variable length shift register consisting of a ring counter and a memory.

According to the present invention, there is provided a ring counter that synchronously generates M address signals according to a specified shift amount M, a memory that writes input data in accordance with the address signal, and a latch that outputs the output signal from the memory. A variable length shift register including a register for outputting and outputting is obtained.

The variable length shift register of this invention can be used in recent ICRAMs.
Rapid advances in technology have made it possible to use large-capacity, high-speed, low-cost, and highly reliable memories, and because the circuit configuration is simple, not only can the number of ICs be reduced, but also high speed and high reliability can be achieved. This is particularly effective for large-scale two-dimensional shift registers used in pre-processing circuits such as image processing. This invention will be explained below using the drawings.

FIG. 2 shows an embodiment of the present invention. A pongee line indicates one signal line, and a thick line indicates multiple signal lines. The subtracter 33 subtracts the "1" signal 106 from the designated shift amount M signal 102 from an external device (not shown), and outputs the (M-1) signal 105. Comparator 34
is the (M-1) signal 105 which is the output of the subtracter 33
and an address signal 104 which is the output of a counter 32 described later, and if they match, a load signal 205 is output.
The counter 32 is incremented by a clock signal 300 from an external device, and when the content of the counter 32 reaches (M-1), the load signal 203 from the comparator 34 and "0" are input.
” signal 107, the clock signal 300 becomes “0” at the next clock time. That is, the counter 32 becomes “0” at the next clock time of the clock signal 300.
..., (M-2), (M-1), 0, 1, 2... and 0 ~ (M
An address signal 104 having M values of -1) is output with a period of M clocks. The operation of this counter 32 is as follows:
It is well known as digital circuit technology. memory 3
0 is the address signal 1 by a timing signal (hereinafter referred to as CE signal-chip enable signal) 200 that enables data entry and writing into the memory 30 from an external device.
A timing signal (hereinafter referred to as WE signal - write enable) that specifies to output the contents of the address specified by 04 as the read signal 103 and write the CE signal 200 from the external device and the input data signal 100 to the memory 30. The input data signal 100 from the external device is sent to the address specified by the address signal 104 by the signal 201.
write to. The register 31 latches the output signal 103 from the memory 30 with the data set signal 202 from the external device, and outputs the output data signal 101 to the external device. The timing signals associated with memory 30, ie, CE signal 200, WE signal 201, and data set signal 202, are well known in digital circuit technology using memory. FIG. 3 is a time chart showing the main operations of the embodiment shown in FIG.

The address signal 104 has a cycle of 0 to (M-1) due to the clock signal 300 and the load signal 203. Since the input data signal 100 is "1" and the address signal 104 is "0" at the first clock of the period P, "1" is written to address 0 of the memory 30 by the CE signal 200 and the WE signal 201. is written. Similarly, at the second clock, memory 3
“0” at address 1 of 0. is written. Now, the next cycle (
Since the address signal 104 is "0" due to the CE signal 200 indicated by the R mark at the first clock of P11) (that is, after M clocks of the first clock of period P), the address signal 104 is "0". The contents of the address, that is, "1" written at the first clock of synchronization P, is output as a read signal 103, and is latched in the register 31 by the data set signal 202, so that the output data signal 101 is obtained. On the other hand, CE signal 2 indicated by W mark
Since the input data signal 100 is "0" due to the WE signal 201 and the WE signal 201, "0" is written to address 0 of the memory 30. Similarly, the address signal 104 is set to "1" by the CE signal 200 indicated by the R mark at the second clock time of (P11).
Therefore, the contents of address 1 of the memory 30 are retrieved and "0" is obtained from the register 30 as the output data signal 101, and the data input signal is "1" due to the CE signal 200 and WE signal 201 indicated by the W mark. Because there is, 1 of 30 memory
“1” is written to the address. That is, at each time,
The memory 30 is first read out by the CE signal 200 indicated by the R mark at the address specified by the address signal 104.
After that, CE signal 201 and WE signal 201 indicated by W mark
Input data signal 100 is written by. Clock signal 30 or more, input data signal 100 and output data signal 10
1, it is clear that the same operation as a general shift register with a shift amount M is realized.

FIG. 4 schematically shows one embodiment of FIG. 2, centering on the memory 30.

For example, an IKBit ICRAM is shown as the memory 30. In the case of a shift register designated with a shift amount M, the memory 30 is synchronously and sequentially addressed from address 0 to address (M-1). After the contents of address i specified by address signal 104 are latched into register 31 by data cut signal 202 and output data signal 101 is obtained, input data signal 100 is written to address i.
The content written to address i is outputted when address signal 104 specifies address i again one cycle later, and is latched in register 31 to obtain output data signal 101. Now, in the circuit configuration of the embodiment shown in FIG.
2. The subtracter 33 and the comparator 34 form a ring counter having a value of 0 to (M-1) using the designated shift amount M signal 102 as a parameter.

The contents of the address signal 104 for the memory 30 range from 0 to
It is not necessary to have only (M-1) values, but it is a necessary and sufficient condition that it has M values and is periodic. Figure 5 shows
2 shows another embodiment for forming a ring counter.

The subtracter 33 receives a “1” signal 1 from the shift amount M signal 102.
06 is subtracted and (M-1) signal 105 is output. The inverter 35 receives the (M-1) signal 1 from the subtracter 33.
Impart 05. The counter 32 is The count is increased by the check signal 300, and the contents of the counter 32 are all “1”.
When this happens, an overflow signal 203 is output. The overflow signal 203 is connected to the load terminal of the counter 32.
Load the output signal 107 from 5. That is, the second
An output signal 107 from the inverter 35 is loaded into the counter 32 as a substitute for the "0" signal 107 in the figure. The maximum value of the counter 32, that is, the overflow signal 20
If the content of the counter 32 where 3 occurs is 1023, then
The counter 32 cycles through M values from 1023-(M-1) to 1023. Overflow signal 203 has the same function as load signal 203 generated from comparator 34 in FIG. FIG. 6a shows the pattern of the memory 30 addressed by the ring counter consisting of the counter 32, subtracter 33 and comparator 34 in FIG.

The shaded area indicates that M addresses from address 0 to address (M-1) are addressed. Figure 6b shows the fifth
Counter 32, subtracter 33, and inverter 35 shown in the figure
Memory 3 addressed by a ring counter consisting of
0 pattern is shown. This indicates that M addresses from the shaded area 1023-(M-1) to 1023 are addressed. Here, two methods of addressing the memory 30 have been described.
A ring counter in which M different addresses are addressed by the signal 102 satisfies the function of the present invention.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional generally used variable length shift register, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a block diagram of the main parts of the block diagram of FIG. 2. A diagram showing a time chart, Fig. 4 is a schematic diagram of the operating function of Fig. 2, Fig. 5 is another embodiment of the ring counter, and Fig. 6 shows the operating function of Fig. 2 and the operation of Fig. 5. It is a comparison diagram of functions. 10 to 19 are multiplexers, 20 to 29 are shift registers, 30 is a memory, 31 is a register, 32 is a counter, 33 is a subtracter, 34 is a comparator, and 35 is an inverter. 2 O figure O 2 figure O 4 figure O 3 figure O 5 figure 6 figure

Claims (1)

[Scope of Claims] 1. A digital variable length shift register including a ring counter that periodically generates an address signal having M values according to a specified shift amount M, and a ring counter that is connected to the ring counter and that receives the address signal. After outputting a read signal according to the first timing signal inputted with the contents of the addressed address, the input data signal inputted at the same address is read out by the first timing signal and the second timing signal. A variable length shift register including a memory to which data is written using a timing signal, and a register that obtains an output data signal by latching a read signal output from a memory connected to the memory using a third timing signal. 2 Set the ring counter to “1” from the specified shift amount M
a subtracter that subtracts the number, a comparator that compares the output of the subtracter with an address signal of the output of the counter described later and outputs a matching signal, and increases the number based on the input clock signal,
2. The variable length shift register according to claim 1, further comprising a counter that becomes "0" in response to a match signal from the comparator. 3 Set the ring counter to “1” from the specified shift amount M
an inverter that inverts the output of the subtracter; an inverter that inverts the output of the subtracter; and an inverter that inverts the output of the subtracter. The first claim is a counter that loads the output.
Variable length shift register as described in section.